8253/8254 PIT - Programmable Interval Timer

   Port 40h, 8253 Counter 0 Time of Day Clock (normally mode 3)
   Port 41h, 8253 Counter 1 RAM Refresh Counter (normally mode 2)
   Port 42h, 8253 Counter 2 Cassette and Speaker Functions
   Port 43h, 8253 Mode Control Register, data format:


   │7│6│5│4│3│2│1│0│  Mode Control Register
    │ │ │ │ │ │ │ └──── 0=16 binary counter, 1=4 decade BCD counter
    │ │ │ │ └─┴─┴───── counter mode bits
    │ │ └─┴────────── read/write/latch format bits
    └─┴───────────── counter select bits (also 8254 read back command)

   Bits
    76 Counter Select Bits

    00  select counter 0
    01  select counter 1
    10  select counter 2
    11  read back command (8254 only, illegal on 8253, see below)

   Bits
    54  Read/Write/Latch Format Bits

    00  latch present counter value
    01  read/write of MSB only
    10  read/write of LSB only
    11  read/write LSB, followed by write of MSB


   Bits
   321  Counter Mode Bits

   000  mode 0, interrupt on terminal count;  countdown, interrupt,
        then wait for a new mode or count; loading a new count in
        the middle of a count stops the countdown
   001  mode 1, programmable one-shot; countdown with optional
        restart; reloading the counter will not affect the
        countdown until after the following trigger
   010  mode 2, rate generator; generate one pulse after 'count' CLK
        cycles; output remains high until after the new countdown has
        begun; reloading the count mid-period does not take affect
        until after the period
   011  mode 3, square wave rate generator; generate one pulse after
        'count' CLK cycles; output remains high until 1/2 of the next
        countdown; it does this by decrementing by 2 until zero, at
        which time it lowers the output signal, reloads the counter
        and counts down again until interrupting at 0; reloading the
        count mid-period does not take affect until after the period
   100  mode 4, software triggered strobe; countdown with output high
        until counter zero;  at zero output goes low for one CLK
        period;  countdown is triggered by loading counter; reloading
        counter takes effect on next CLK pulse
   101  mode 5, hardware triggered strobe; countdown after triggering
        with output high until counter zero; at zero output goes low
        for one CLK period

   Read Back Command Format  (8254 only)

   │7│6│5│4│3│2│1│0│ Read Back Command (written to Mode Control Reg)
    │ │ │ │ │ │ │ └─── must be zero
    │ │ │ │ │ │ └──── select counter 0
    │ │ │ │ │ └───── select counter 1
    │ │ │ │ └────── select counter 2
    │ │ │ └─────── 0 = latch status of selected counters
    │ │ └──────── 0 = latch count of selected counters
    └─┴───────── 11 = read back command


   Read Back Command Status (8254 only, read from counter register)

   │7│6│5│4│3│2│1│0│  Read Back Command Status
    │ │ │ │ │ │ │ └─── 0=16 binary counter, 1=4 decade BCD counter
    │ │ │ │ └─┴─┴──── counter mode bits (see Mode Control Reg above)
    │ │ └─┴───────── read/write/latch format (see Mode Control Reg)
    │ └──────────── 1=null count (no count set), 0=count available
    └───────────── state of OUT pin (1=high, 0=low)