/*
Copyright (C) Magna Carta Software, Inc. 1988, 1990. All Rights Reserved.
C COMMUNICATIONS TOOLKIT
Z80SIO.H -- C Communications Toolkit header file for Z80SIO/DART USART
*/
#if !defined(Z80SIO_H_INCLUDED)
#if !defined(COMM_H_INCLUDED)
#include <comm.h>
#endif
#define Z80SIO 2 /* Denotes a Z80SIO/DART family U(S)ART */
/* INTERRUPT TYPES USED IN ENABLE COMMANDS */
#define UZ80_ES 0X1 /* write to WR1 */
#define UZ80_TX_ALL 0X2 /* write to WR1 */
#define UZ80_RX_FIRST_CHARACTER 0X8 /* write to WR1 */
#define UZ80_RX_ALL_SPECIAL_RECEIVE 0X10 /* write to WR1 */
#define UZ80_RX_ALL 0X18 /* write to WR1 */
/* Z-80 SIO COMMANDS (issued to WR0) */
#define UZ80_ES_RESET 0X10 /* external/status reset to WR0 */
#define UZ80_CH_RESET 0X18 /* channel reset to WR0 */
#define UZ80_TX_RESET 0X28 /* transmit int. pending reset */
#define UZ80_ER_RESET 0X30 /* error reset to WR0 */
#define UZ80_RX_CRC_RESET 0X40 /* reset RX CRC checker */
#define UZ80_TX_CRC_RESET 0X80 /* reset TX CRC checker */
#define UZ80_TX_EOM_RESET 0XC0 /* reset TX underrun/EOM latch */
/* DATA FORMATS */
#define UZ80_RX_DATA5 0
#define UZ80_RX_DATA6 0X80 /* 1000 0000 */
#define UZ80_RX_DATA7 0X40 /* 0100 0000 */
#define UZ80_RX_DATA8 0XC0 /* 1100 0000 */
#define UZ80_TX_DATA5 0
#define UZ80_TX_DATA6 0X40 /* 0100 0000 */
#define UZ80_TX_DATA7 0X20 /* 0010 0000 */
#define UZ80_TX_DATA8 0X60 /* 0110 0000 */
#define UZ80_STOPBITS0 0
#define UZ80_STOPBITS1 0X04 /* 0000 0100 */
#define UZ80_STOPBITS15 0X08 /* 0000 1000 */
#define UZ80_STOPBITS2 0X0C /* 0000 1100 */
#define UZ80_PARITY_NONE 0
#define UZ80_PARITY_ODD 1 /* 0000 0001 */
#define UZ80_PARITY_EVEN 3 /* 0000 0011 */
#define UZ80_BISYNC 0X10 /* 0001 0000 */
/* REGISTER NAMES */
#define WR0 0 /* write register 0 of Z80SIO */
#define WR1 1 /* write register 1 of Z80SIO */
#define WR2 2 /* write register 2 of Z80SIO */
#define WR3 3 /* write register 3 of Z80SIO */
#define WR4 4 /* write register 4 of Z80SIO */
#define WR5 5 /* write register 5 of Z80SIO */
#define WR6 6 /* write register 6 of Z80SIO */
#define WR7 7 /* write register 7 of Z80SIO */
#define RR0 (0X80 | 0) /* read register 0 of Z80SIO */
#define RR1 (0X80 | 1) /* read register 1 of Z80SIO */
#define RR2 (0X80 | 2) /* read register 2 of Z80SIO */
/* MASKS FOR SPECIFIC REGISTERS */
#define CHANNEL_A_ADDR -1 /* address of channel A ctl. */
#define CHANNEL_B_ADDR 0 /* address of channel B ctl. */
#define UZ80_RX_MASK 1 /* UART receive character mask */
#define UZ80_TX_MASK 4 /* UART transmit ready mask */
/* WRITE REGISTER 3 -- */
#define UZ80_RX_ENABLE 0x01 /* enable receive mask WR3 */
#define UZ80_SYNC_INHIBIT 0X02 /* inhibit load of RX SYNC */
#define UZ80_RX_CRC_ENABLE 0X08 /* enable RX CRC */
#define UZ80_HUNT_ENTER 0X10 /* enter hunt phase bit */
#define UZ80_AUTO_ENABLE 0X20 /* auto enable transmit */
#define UZ80_RX_DATABITS_MASK 0XC0 /* wr3 = 11000000 */
/* WRITE REGISTER 4 -- */
#define UZ80_PARITY_MASK 0X03 /* wr4 = 00000011 */
#define UZ80_STOPBITS_MASK 0X0C /* wr4 = 00001100 */
#define UZ80_SYNC_MASK 0X30 /* Z80 reference clock speed WR4*/
#define UZ80_CLOCK_MASK 0XC0 /* Z80 reference clock speed WR4*/
/* WRITE REGISTER 5 -- */
#define UZ80_TX_CRC_ENABLE 0X01 /* wr5 = 00000001 */
#define UZ80_RTS_MASK 0X02 /* wr5 = 00000010 */
#define UZ80_CRC16_MASK 0X04 /* wr5 = 00000010 */
#define UZ80_TX_ENABLE 0X08 /* enable transmit mask WR5 */
#define UZ80_BREAK_MASK 0X10 /* wr5 = 00010000 */
#define UZ80_TX_DATABITS_MASK 0X60 /* wr5 = 01100000 */
#define UZ80_DTR_MASK 0X80 /* wr5 = 10000000 */
/* READ REGISTERS */
#define UZ80_RI_MASK 0X10 /* modem status reg. 01000000 */
#define UZ80_CTS_MASK 0X20 /* DCD mask 00100000 */
#define UZ80_DCD_MASK 0X08 /* DCD mask 00001000 */
/* REFERENCE CLOCK SPEEDS */
#define X1 0 /* Z80 x1 reference clock */
#define X16 0X40 /* Z80 x16 reference clock */
#define X32 0X80 /* Z80 x32 reference clock */
#define X64 0XC0 /* Z80 x64 reference clock */
short FCALL_ uz80_deinit_(COMM_PORT *p);
short FCALL_ uz80_deinstall_ipr_(COMM_PORT *p, WORD itype);
short FCALL_ uz80_disable_comm_int_(COMM_PORT *p_port, WORD int_type);
short FCALL_ uz80_enable_comm_int_(COMM_PORT *p_port, WORD int_type);
short FCALL_ uz80_get_(COMM_PORT *p, short cmd);
short FCALL_ uz80_get_databits_(COMM_PORT *p_port, short direction);
short FCALL_ uz80_get_stopbits_(COMM_PORT *p_port);
short FCALL_ uz80_get_rr_(COMM_PORT *p, WORD reg);
short FCALL_ uz80_get_wr_(COMM_PORT *p, short reg);
short FCALL_ uz80_init(COMM_PORT *p, WORD cha_addr, WORD addr, long speed, WORD databits,
WORD parity, WORD stopbits);
short FCALL_ uz80_install_ipr_(COMM_PORT *p, WORD type, void FAR_ *fn, BYTE FAR_ *buf, WORD len);
short FCALL_ uz80_int_set_(COMM_PORT *p_port, WORD irq_num, WORD state);
short FCALL_ uz80_mod_reg_(COMM_PORT *p_port, WORD reg, WORD value, WORD mask);
short FCALL_ uz80_read_(COMM_PORT *p_port);
void INTERRUPT_ uz80_rx_int_(void);
short FCALL_ uz80_rxstat_(COMM_PORT *p_port);
short FCALL_ uz80_set_(COMM_PORT *p, short cmd, short value);
short FCALL_ uz80_send_break_(COMM_PORT *p_port);
void FCALL_ uz80_set_clock(COMM_PORT *p_port, WORD speed);
short FCALL_ uz80_set_databits_(COMM_PORT *p_port, short value, short direction);
short FCALL_ uz80_set_parity_(COMM_PORT *p_port, short value);
void FCALL_ uz80_set_reg_(COMM_PORT *p_port, short reg, short value);
short FCALL_ uz80_set_rx_xlat_(COMM_PORT *p, short item, short value);
short FCALL_ uz80_set_speed_(COMM_PORT *p_port, long value);
short FCALL_ uz80_set_stopbits_(COMM_PORT *p_port, short value);
void INTERRUPT_ uz80_tx_int_(void);
short FCALL_ uz80_set_tx_xlat_(COMM_PORT *p, short item, short value);
short FCALL_ uz80_txstat_(COMM_PORT *p_port);
void FCALL_ uz80_write_(COMM_PORT *p_port, WORD c);
#define Z80SIO_H_INCLUDED
#endif
