============================================================================================================================================== OFFSET 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F ---------------------------------------------------------------------------------------------------------------------------------------------- 00000000 DB A5 2D 00 78 40 09 04 00 00 08 00 2D 00 00 00 00 00 00 00 00 00 00 00 80 01 00 00 0E 30 01 00 █Ñ-.x@○♦..◘.-...........Ç☺..♫0☺. 00000020 52 B6 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 FF 2C 01 00 41 00 00 00 4C 01 00 00 R╢☺................. ,☺.A...L☺.. 00000040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 A4 01 00 6E 08 00 A4 .........................ñ☺.n◘.ñ 00000060 01 00 6E 08 6E AC 01 00 0A 00 78 AC 01 00 0C 00 B8 AE 01 00 00 00 B8 AE 01 00 00 00 B8 AE 01 00 ☺.n◘n¼☺.◙.x¼☺.♀.╕«☺...╕«☺...╕«☺. 00000080 22 00 DA AE 01 00 42 02 1C B1 01 00 00 00 1C B1 01 00 00 00 1C B1 01 00 00 00 1C B1 01 00 28 00 ".┌«☺.B☻∟▒☺...∟▒☺...∟▒☺...∟▒☺.(. 000000A0 44 B1 01 00 7C 00 C0 B1 01 00 D0 00 1C B1 01 00 00 00 90 B2 01 00 95 00 25 B3 01 00 BE 00 E3 B3 D▒☺.|.└▒☺.╨.∟▒☺...É▓☺.ò.%│☺.╛.π│ 000000C0 01 00 4C 00 2F B4 01 00 00 00 2F B4 01 00 00 00 2F B4 01 00 00 00 2F B4 01 00 2D 00 5C B4 01 00 ☺.L./┤☺.../┤☺.../┤☺.../┤☺.-.\┤☺. 000000E0 28 00 84 B4 01 00 1C 00 A0 B4 01 00 02 00 A2 B4 01 00 00 00 A2 B4 01 00 00 00 A2 B4 01 00 25 00 (.ä┤☺.∟.á┤☺.☻.ó┤☺...ó┤☺...ó┤☺.%. 00000100 C7 B4 01 00 00 01 C7 B5 01 00 00 00 C7 B5 01 00 1E 00 E5 B5 01 00 34 00 19 B6 01 00 39 00 E5 B5 ╟┤☺..☺╟╡☺...╟╡☺.▲.σ╡☺.4.↓╢☺.9.σ╡ 00000120 01 00 00 00 84 AC 01 00 34 02 00 00 00 00 00 00 E5 B5 01 00 00 00 E5 B5 01 00 00 00 00 00 9C 00 ☺...ä¼☺.4☻......σ╡☺...σ╡☺.....£. 00000140 B0 00 14 00 22 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ░.¶."........................... 00000160 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................................ 00000180 41 50 2D 35 30 30 0D 0A 0D 0A 41 70 70 6C 69 63 61 74 69 6F 6E 0D 0A 4E 6F 74 65 0D 0A 0D 0A 0D AP-500♪◙♪◙Application♪◙Note♪◙♪◙♪ 000001A0 0A 4F 70 74 69 6D 69 7A 61 74 69 6F 6E 73 20 66 6F 72 20 49 6E 74 65 6C 27 73 20 0D 0A 33 32 2D ◙Optimizations for Intel's ♪◙32- 000001C0 42 69 74 20 50 72 6F 63 65 73 73 6F 72 73 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A Bit Processors♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙ 000001E0 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A ♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙ 00000200 0D 0A 0D 0A 46 65 62 72 75 61 72 79 20 31 39 39 34 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 54 68 65 ♪◙♪◙February 1994♪◙♪◙♪◙♪◙♪◙♪◙The 00000220 20 66 6F 6C 6C 6F 77 69 6E 67 20 61 72 65 20 74 72 61 64 65 6D 61 72 6B 73 20 6F 66 20 49 6E 74 following are trademarks of Int 00000240 65 6C 20 43 6F 72 70 6F 72 61 74 69 6F 6E 20 61 6E 64 20 6D 61 79 20 6F 6E 6C 79 20 62 65 20 75 el Corporation and may only be u 00000260 73 65 64 20 74 6F 20 69 64 65 6E 74 69 66 79 20 49 6E 74 65 6C 20 70 72 6F 64 75 63 74 73 3A 0D sed to identify Intel products:♪ 00000280 0A 49 6E 74 65 6C 2C 20 49 6E 74 65 6C 33 38 36 2C 20 49 6E 74 65 6C 34 38 36 2C 20 69 34 38 36 ◙Intel, Intel386, Intel486, i486 000002A0 2C 20 61 6E 64 20 50 65 6E 74 69 75 6D 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D , and Pentium♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪ 000002C0 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D ◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪ 000002E0 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 49 6E 74 65 6C 20 43 6F 72 70 6F 72 61 74 69 6F 6E 20 6D ◙♪◙♪◙♪◙♪◙♪◙♪◙Intel Corporation m 00000300 61 6B 65 73 20 6E 6F 20 77 61 72 72 61 6E 74 79 20 66 6F 72 20 74 68 65 20 75 73 65 20 6F 66 20 akes no warranty for the use of 00000320 69 74 73 20 70 72 6F 64 75 63 74 73 20 61 6E 64 20 61 73 73 75 6D 65 73 20 6E 6F 20 72 65 73 70 its products and assumes no resp 00000340 6F 6E 73 69 62 69 6C 69 74 79 20 66 6F 72 20 61 6E 79 20 65 72 72 6F 72 73 20 77 68 69 63 68 20 onsibility for any errors which 00000360 6D 61 79 20 61 70 70 65 61 72 20 69 6E 20 74 68 69 73 20 64 6F 63 75 6D 65 6E 74 20 6E 6F 72 20 may appear in this document nor 00000380 64 6F 65 73 20 69 74 20 6D 61 6B 65 20 61 20 63 6F 6D 6D 69 74 6D 65 6E 74 20 74 6F 20 75 70 64 does it make a commitment to upd 000003A0 61 74 65 20 74 68 65 20 69 6E 66 6F 72 6D 61 74 69 6F 6E 20 63 6F 6E 74 61 69 6E 65 64 20 68 65 ate the information contained he 000003C0 72 65 69 6E 2E 0D 0A 0D 0A 49 6E 74 65 6C 20 72 65 74 61 69 6E 73 20 74 68 65 20 72 69 67 68 74 rein.♪◙♪◙Intel retains the right 000003E0 20 74 6F 20 6D 61 6B 65 20 63 68 61 6E 67 65 73 20 74 6F 20 74 68 65 73 65 20 73 70 65 63 69 66 to make changes to these specif 00000400 69 63 61 74 69 6F 6E 73 20 61 74 20 61 6E 79 20 74 69 6D 65 2C 20 77 69 74 68 6F 75 74 20 6E 6F ications at any time, without no 00000420 74 69 63 65 2E 0D 0A 0D 0A 43 6F 6E 74 61 63 74 20 79 6F 75 72 20 6C 6F 63 61 6C 20 49 6E 74 65 tice.♪◙♪◙Contact your local Inte 00000440 6C 20 73 61 6C 65 73 20 6F 66 66 69 63 65 20 6F 72 20 79 6F 75 72 20 64 69 73 74 72 69 62 75 74 l sales office or your distribut 00000460 6F 72 20 74 6F 20 6F 62 74 61 69 6E 20 74 68 65 20 6C 61 74 65 73 74 20 73 70 65 63 69 66 69 63 or to obtain the latest specific 00000480 61 74 69 6F 6E 73 20 62 65 66 6F 72 65 20 70 6C 61 63 69 6E 67 20 79 6F 75 72 20 70 72 6F 64 75 ations before placing your produ 000004A0 63 74 20 6F 72 64 65 72 2E 0D 0A 0D 0A 4D 44 53 20 69 73 20 61 6E 20 6F 72 64 65 72 69 6E 67 20 ct order.♪◙♪◙MDS is an ordering 000004C0 63 6F 64 65 20 6F 6E 6C 79 20 61 6E 64 20 69 73 20 6E 6F 74 20 75 73 65 64 20 61 73 20 61 20 70 code only and is not used as a p 000004E0 72 6F 64 75 63 74 20 6E 61 6D 65 20 6F 72 20 74 72 61 64 65 6D 61 72 6B 20 6F 66 20 49 6E 74 65 roduct name or trademark of Inte 00000500 6C 20 43 6F 72 70 6F 72 61 74 69 6F 6E 2E 0D 0A 0D 0A 49 6E 74 65 6C 20 43 6F 72 70 6F 72 61 74 l Corporation.♪◙♪◙Intel Corporat 00000520 69 6F 6E 20 61 6E 64 20 49 6E 74 65 6C 27 73 20 46 41 53 54 50 41 54 48 20 61 72 65 20 6E 6F 74 ion and Intel's FASTPATH are not 00000540 20 61 66 66 69 6C 69 61 74 65 64 20 77 69 74 68 20 4B 69 6E 65 74 69 63 73 2C 20 61 20 64 69 76 affiliated with Kinetics, a div 00000560 69 73 69 6F 6E 20 6F 66 20 45 78 63 65 6C 61 6E 2C 20 49 6E 63 2E 20 6F 72 20 69 74 20 46 41 53 ision of Excelan, Inc. or it FAS 00000580 54 50 41 54 48 20 74 72 61 64 65 6D 61 72 6B 20 6F 72 20 70 72 6F 64 75 63 74 73 2E 0D 0A 0D 0A TPATH trademark or products.♪◙♪◙ 000005A0 2A 20 20 4F 74 68 65 72 20 62 72 61 6E 64 73 20 61 6E 64 20 6E 61 6D 65 73 20 61 72 65 20 74 68 * Other brands and names are th 000005C0 65 20 70 72 6F 70 65 72 74 79 20 6F 66 20 74 68 65 69 72 20 72 65 73 70 65 63 74 69 76 65 20 6F e property of their respective o 000005E0 77 6E 65 72 73 2E 0D 0A 0D 0A 41 64 64 69 74 69 6F 6E 61 6C 20 63 6F 70 69 65 73 20 6F 66 20 74 wners.♪◙♪◙Additional copies of t 00000600 68 69 73 20 64 6F 63 75 6D 65 6E 74 20 6F 72 20 6F 74 68 65 72 20 49 6E 74 65 6C 20 6C 69 74 65 his document or other Intel lite 00000620 72 61 74 75 72 65 20 6D 61 79 20 62 65 20 6F 62 74 61 69 6E 65 64 20 66 72 6F 6D 3A 0D 0A 0D 0A rature may be obtained from:♪◙♪◙ 00000640 09 09 49 6E 74 65 6C 20 43 6F 72 70 6F 72 61 74 69 6F 6E 0D 0A 09 09 4C 69 74 65 72 61 74 75 72 ○○Intel Corporation♪◙○○Literatur 00000660 65 20 53 61 6C 65 73 0D 0A 09 09 50 2E 4F 2E 20 42 6F 78 20 37 36 34 31 0D 0A 09 09 4D 74 2E 20 e Sales♪◙○○P.O. Box 7641♪◙○○Mt. 00000680 50 72 6F 73 70 65 63 74 2C 20 49 4C 20 20 36 30 30 35 36 2D 37 36 34 31 0D 0A 0D 0A 09 09 6F 72 Prospect, IL 60056-7641♪◙♪◙○○or 000006A0 20 63 61 6C 6C 20 31 2D 38 30 30 2D 38 37 39 2D 34 36 38 33 0D 0A 0D 0A 0D 0A 0D 0A E3 20 49 4E call 1-800-879-4683♪◙♪◙♪◙♪◙π IN 000006C0 54 45 4C 20 43 4F 52 50 4F 52 41 54 49 4F 4E 2C 20 31 39 39 33 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D TEL CORPORATION, 1993♪◙♪◙♪◙♪◙♪◙♪ 000006E0 0A 0D 0A 0D 0A 54 61 62 6C 65 20 6F 66 20 43 6F 6E 74 65 6E 74 73 0D 0A 0D 0A 0D 0A 13 54 4F 43 ◙♪◙♪◙Table of Contents♪◙♪◙♪◙‼TOC 00000700 20 5C 6F 14 31 2E 20 20 49 6E 74 72 6F 64 75 63 74 69 6F 6E 20 09 31 0D 0A 0D 0A 32 2E 20 20 4F \o¶1. Introduction ○1♪◙♪◙2. O 00000720 76 65 72 76 69 65 77 20 6F 66 20 49 6E 74 65 6C 33 38 36 99 2C 20 49 6E 74 65 6C 34 38 36 99 2C verview of Intel386Ö, Intel486Ö, 00000740 20 50 65 6E 74 69 75 6D 99 20 50 72 6F 63 65 73 73 6F 72 73 09 31 0D 0A 32 2E 31 2E 20 54 68 65 PentiumÖ Processors○1♪◙2.1. The 00000760 20 49 6E 74 65 6C 33 38 36 20 50 72 6F 63 65 73 73 6F 72 09 31 0D 0A 32 2E 31 2E 31 2E 20 20 49 Intel386 Processor○1♪◙2.1.1. I 00000780 6E 73 74 72 75 63 74 69 6F 6E 20 50 72 65 66 65 74 63 68 65 72 09 31 0D 0A 32 2E 31 2E 32 2E 20 nstruction Prefetcher○1♪◙2.1.2. 000007A0 20 49 6E 73 74 72 75 63 74 69 6F 6E 20 44 65 63 6F 64 65 72 09 31 0D 0A 32 2E 31 2E 33 2E 20 20 Instruction Decoder○1♪◙2.1.3. 000007C0 45 78 63 75 74 69 6F 6E 20 43 6F 72 65 09 31 0D 0A 32 2E 32 2E 20 54 68 65 20 49 6E 74 65 6C 34 Excution Core○1♪◙2.2. The Intel4 000007E0 38 36 20 70 72 6F 63 65 73 73 6F 72 09 31 0D 0A 32 2E 32 2E 31 2E 20 20 49 6E 74 65 67 65 72 20 86 processor○1♪◙2.2.1. Integer 00000800 50 69 70 65 6C 69 6E 65 09 32 0D 0A 32 2E 32 2E 32 2E 20 20 4F 6E 2D 43 68 69 70 20 43 61 63 68 Pipeline○2♪◙2.2.2. On-Chip Cach 00000820 65 09 32 0D 0A 32 2E 32 2E 33 2E 20 20 4F 6E 2D 43 68 69 70 20 46 6C 6F 61 74 69 6E 67 2D 50 6F e○2♪◙2.2.3. On-Chip Floating-Po 00000840 69 6E 74 20 55 6E 69 74 09 32 0D 0A 32 2E 33 2E 20 54 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F int Unit○2♪◙2.3. The Pentium pro 00000860 63 65 73 73 6F 72 09 32 0D 0A 32 2E 33 2E 31 2E 20 20 49 6E 74 65 67 65 72 20 50 69 70 65 6C 69 cessor○2♪◙2.3.1. Integer Pipeli 00000880 6E 65 73 09 33 0D 0A 32 2E 33 2E 32 2E 20 20 43 61 63 68 65 73 09 33 0D 0A 32 2E 33 2E 33 2E 20 nes○3♪◙2.3.2. Caches○3♪◙2.3.3. 000008A0 20 49 6E 73 74 72 75 63 74 69 6F 6E 20 50 72 65 66 65 74 63 68 65 72 09 33 0D 0A 32 2E 33 2E 34 Instruction Prefetcher○3♪◙2.3.4 000008C0 2E 20 20 42 72 61 6E 63 68 20 54 61 72 67 65 74 20 42 75 66 66 65 72 09 33 0D 0A 32 2E 33 2E 35 . Branch Target Buffer○3♪◙2.3.5 000008E0 2E 20 20 50 69 70 65 6C 69 6E 65 64 20 46 6C 6F 61 74 69 6E 67 2D 50 6F 69 6E 74 20 55 6E 69 74 . Pipelined Floating-Point Unit 00000900 09 33 0D 0A 33 2E 20 20 49 6E 74 65 67 65 72 20 45 78 61 6D 70 6C 65 73 09 34 0D 0A 33 2E 31 2E ○3♪◙3. Integer Examples○4♪◙3.1. 00000920 20 43 6F 64 65 20 53 65 71 75 65 6E 63 65 20 31 2C 20 49 6E 74 65 6C 34 38 36 20 50 72 6F 63 65 Code Sequence 1, Intel486 Proce 00000940 73 73 6F 72 09 35 0D 0A 33 2E 32 2E 20 43 6F 64 65 20 53 65 71 75 65 6E 63 65 20 31 2C 20 50 65 ssor○5♪◙3.2. Code Sequence 1, Pe 00000960 6E 74 69 75 6D 20 50 72 6F 63 65 73 73 6F 72 09 36 0D 0A 33 2E 33 2E 20 43 6F 64 65 20 53 65 71 ntium Processor○6♪◙3.3. Code Seq 00000980 75 65 6E 63 65 20 32 2C 20 49 6E 74 65 6C 34 38 36 20 50 72 6F 63 65 73 73 6F 72 09 36 0D 0A 33 uence 2, Intel486 Processor○6♪◙3 000009A0 2E 34 2E 20 43 6F 64 65 20 53 65 71 75 65 6E 63 65 20 32 2C 20 50 65 6E 74 69 75 6D 20 50 72 6F .4. Code Sequence 2, Pentium Pro 000009C0 63 65 73 73 6F 72 09 37 0D 0A 33 2E 35 2E 20 43 6F 64 65 20 53 65 71 75 65 6E 63 65 20 33 2C 20 cessor○7♪◙3.5. Code Sequence 3, 000009E0 49 6E 74 65 6C 34 38 36 20 50 72 6F 63 65 73 73 6F 72 09 37 0D 0A 33 2E 36 2E 20 43 6F 64 65 20 Intel486 Processor○7♪◙3.6. Code 00000A00 53 65 71 75 65 6E 63 65 20 33 2C 20 50 65 6E 74 69 75 6D 20 50 72 6F 63 65 73 73 6F 72 09 37 0D Sequence 3, Pentium Processor○7♪ 00000A20 0A 34 2E 20 20 43 6F 64 65 20 47 65 6E 65 72 61 74 69 6F 6E 20 53 74 72 61 74 65 67 79 09 39 0D ◙4. Code Generation Strategy○9♪ 00000A40 0A 0D 0A 35 2E 20 20 42 6C 65 6E 64 65 64 20 43 6F 64 65 20 47 65 6E 65 72 61 74 69 6F 6E 20 43 ◙♪◙5. Blended Code Generation C 00000A60 6F 6E 73 69 64 65 72 61 74 69 6F 6E 09 31 30 0D 0A 35 2E 31 2E 20 20 43 68 6F 69 63 65 20 6F 66 onsideration○10♪◙5.1. Choice of 00000A80 20 49 6E 64 65 78 20 56 65 72 73 75 73 20 42 61 73 65 20 52 65 67 69 73 74 65 72 09 31 30 0D 0A Index Versus Base Register○10♪◙ 00000AA0 35 2E 32 2E 20 20 41 64 64 72 65 73 73 69 6E 67 20 4D 6F 64 65 73 20 61 6E 64 20 52 65 67 69 73 5.2. Addressing Modes and Regis 00000AC0 74 65 72 20 55 73 61 67 65 09 31 30 0D 0A 35 2E 33 2E 20 20 50 72 65 66 65 74 63 68 20 42 61 6E ter Usage○10♪◙5.3. Prefetch Ban 00000AE0 64 77 69 64 74 68 09 31 31 0D 0A 35 2E 34 2E 20 20 41 6C 69 67 6E 6D 65 6E 74 09 31 32 0D 0A 35 dwidth○11♪◙5.4. Alignment○12♪◙5 00000B00 2E 34 2E 31 2E 20 20 43 6F 64 65 09 31 32 0D 0A 35 2E 34 2E 32 2E 20 20 44 61 74 61 09 31 32 0D .4.1. Code○12♪◙5.4.2. Data○12♪ 00000B20 0A 35 2E 34 2E 33 2E 20 20 32 2D 42 79 74 65 20 44 61 74 61 09 31 32 0D 0A 35 2E 34 2E 34 2E 20 ◙5.4.3. 2-Byte Data○12♪◙5.4.4. 00000B40 20 34 2D 42 79 74 65 20 44 61 74 61 09 31 32 0D 0A 35 2E 34 2E 35 2E 20 20 38 2D 42 79 74 65 20 4-Byte Data○12♪◙5.4.5. 8-Byte 00000B60 44 61 74 61 09 31 32 0D 0A 35 2E 35 2E 20 20 50 72 65 66 69 78 65 64 20 4F 70 63 6F 64 65 73 09 Data○12♪◙5.5. Prefixed Opcodes○ 00000B80 31 32 0D 0A 35 2E 36 2E 20 20 49 6E 74 65 67 65 72 20 49 6E 73 74 72 75 63 74 69 6F 6E 20 53 63 12♪◙5.6. Integer Instruction Sc 00000BA0 68 65 64 75 6C 69 6E 67 09 31 33 0D 0A 35 2E 36 2E 31 2E 20 20 50 61 69 72 69 6E 67 09 31 33 0D heduling○13♪◙5.6.1. Pairing○13♪ 00000BC0 0A 35 2E 36 2E 32 2E 20 20 49 6E 73 74 72 75 63 74 69 6F 6E 20 53 65 74 20 50 61 69 72 61 62 69 ◙5.6.2. Instruction Set Pairabi 00000BE0 6C 69 74 79 09 31 33 0D 0A 09 35 2E 36 2E 32 2E 31 2E 20 20 55 6E 70 61 69 72 61 62 6C 65 20 49 lity○13♪◙○5.6.2.1. Unpairable I 00000C00 6E 73 74 72 75 63 74 69 6F 6E 73 20 28 4E 50 29 09 31 33 0D 0A 09 35 2E 36 2E 32 2E 32 2E 20 20 nstructions (NP)○13♪◙○5.6.2.2. 00000C20 50 61 69 72 61 62 6C 65 20 49 6E 73 74 72 75 63 74 69 6F 6E 73 20 49 73 73 75 65 64 20 74 6F 20 Pairable Instructions Issued to 00000C40 55 20 6F 72 20 56 20 20 70 69 70 65 73 20 28 55 56 29 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E U or V pipes (UV).............. 00000C60 2E 2E 2E 2E 2E 2E 31 34 0D 0A 09 35 2E 36 2E 32 2E 33 2E 20 20 50 61 69 72 61 62 6C 65 20 49 6E ......14♪◙○5.6.2.3. Pairable In 00000C80 73 74 72 75 63 74 69 6F 6E 73 20 49 73 73 75 65 64 20 6F 74 20 55 20 70 69 70 65 20 28 50 55 29 structions Issued ot U pipe (PU) 00000CA0 09 31 34 0D 0A 09 35 2E 36 2E 32 2E 34 2E 20 20 50 61 69 72 61 62 6C 65 20 49 6E 73 74 72 75 63 ○14♪◙○5.6.2.4. Pairable Instruc 00000CC0 74 69 6F 6E 73 20 49 73 73 75 65 64 20 74 6F 20 56 20 20 70 69 70 65 20 28 50 56 29 09 31 34 0D tions Issued to V pipe (PV)○14♪ 00000CE0 0A 35 2E 36 2E 33 2E 20 20 55 6E 70 61 69 72 61 62 69 6C 69 74 79 20 44 75 65 20 74 6F 20 52 65 ◙5.6.3. Unpairability Due to Re 00000D00 67 69 73 74 65 72 73 09 31 34 0D 0A 35 2E 36 2E 34 2E 20 20 53 70 65 63 69 61 6C 20 50 61 69 72 gisters○14♪◙5.6.4. Special Pair 00000D20 73 09 31 35 0D 0A 35 2E 36 2E 35 2E 20 20 52 65 73 74 72 69 63 74 69 6F 6E 73 20 6F 6E 20 50 61 s○15♪◙5.6.5. Restrictions on Pa 00000D40 69 72 20 45 78 65 63 75 74 69 6F 6E 09 31 36 0D 0A 35 2E 37 2E 20 20 49 6E 74 65 67 65 72 20 49 ir Execution○16♪◙5.7. Integer I 00000D60 6E 73 74 72 75 63 74 69 6F 6E 20 53 65 6C 65 63 74 69 6F 6E 09 31 36 0D 0A 0D 0A 0B 0C 36 2E 20 nstruction Selection○16♪◙♪◙♂♀6. 00000D80 20 50 72 6F 63 65 73 73 6F 72 20 53 70 65 63 69 66 69 63 20 4F 70 74 69 6D 69 7A 61 74 69 6F 6E Processor Specific Optimization 00000DA0 73 09 32 30 0D 0A 36 2E 31 2E 20 20 50 65 6E 74 69 75 6D 20 50 72 6F 63 65 73 73 6F 72 20 46 6C s○20♪◙6.1. Pentium Processor Fl 00000DC0 6F 61 74 69 6E 67 20 50 6F 69 6E 74 09 32 30 0D 0A 36 2E 31 2E 31 2E 20 20 46 6C 6F 61 74 69 6E oating Point○20♪◙6.1.1. Floatin 00000DE0 67 2D 50 6F 69 6E 74 20 45 78 61 6D 70 6C 65 09 32 30 0D 0A 36 2E 31 2E 32 2E 20 20 46 58 43 48 g-Point Example○20♪◙6.1.2. FXCH 00000E00 20 52 75 6C 65 73 20 61 6E 64 20 52 65 67 75 6C 61 74 69 6F 6E 73 09 32 32 0D 0A 36 2E 31 2E 33 Rules and Regulations○22♪◙6.1.3 00000E20 2E 20 20 4D 65 6D 6F 72 79 20 4F 70 65 72 61 6E 64 73 09 32 33 0D 0A 36 2E 31 2E 34 2E 20 20 46 . Memory Operands○23♪◙6.1.4. F 00000E40 6C 6F 61 74 69 6E 67 2D 50 6F 69 6E 74 20 53 74 61 6C 6C 73 09 32 33 0D 0A 37 2E 20 20 53 75 6D loating-Point Stalls○23♪◙7. Sum 00000E60 6D 61 72 79 09 32 36 0D 0A 0D 0A 41 70 70 65 6E 64 69 78 20 41 20 2D 20 49 6E 73 74 72 75 63 74 mary○26♪◙♪◙Appendix A - Instruct 00000E80 69 6F 6E 20 50 61 69 72 69 6E 67 20 53 75 6D 6D 61 72 79 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E ion Pairing Summary............. 00000EA0 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E ................................ 00000EC0 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 2E 41 ...............................A 00000EE0 2D 31 0D 0A 15 09 0C 0D 0A 31 2E 20 49 6E 74 72 6F 64 75 63 74 69 6F 6E 0D 0A 0D 0A 54 68 65 20 -1♪◙§○♀♪◙1. Introduction♪◙♪◙The 00000F00 49 6E 74 65 6C 33 38 36 13 53 59 4D 42 4F 4C 20 32 32 38 20 5C 66 20 22 53 79 6D 62 6F 6C 22 15 Intel386‼SYMBOL 228 \f "Symbol"§ 00000F20 20 41 72 63 68 69 74 65 63 74 75 72 65 20 46 61 6D 69 6C 79 20 72 65 70 72 65 73 65 6E 74 73 20 Architecture Family represents 00000F40 61 20 73 65 72 69 65 73 20 6F 66 20 63 6F 6D 70 61 74 69 62 6C 65 20 70 72 6F 63 65 73 73 6F 72 a series of compatible processor 00000F60 73 20 69 6E 63 6C 75 64 69 6E 67 20 74 68 65 0D 0A 49 6E 74 65 6C 33 38 36 13 53 59 4D 42 4F 4C s including the♪◙Intel386‼SYMBOL 00000F80 20 32 32 38 20 5C 66 20 22 53 79 6D 62 6F 6C 22 15 2C 20 49 6E 74 65 6C 34 38 36 13 53 59 4D 42 228 \f "Symbol"§, Intel486‼SYMB 00000FA0 4F 4C 20 32 32 38 20 5C 66 20 22 53 79 6D 62 6F 6C 22 15 2C 20 61 6E 64 20 74 68 65 20 50 65 6E OL 228 \f "Symbol"§, and the Pen 00000FC0 74 69 75 6D 13 53 59 4D 42 4F 4C 20 32 32 38 20 5C 66 20 22 53 79 6D 62 6F 6C 22 15 20 70 72 6F tium‼SYMBOL 228 \f "Symbol"§ pro 00000FE0 63 65 73 73 6F 72 73 2E 20 20 54 68 65 20 6E 65 77 65 72 20 6D 65 6D 62 65 72 73 20 6F 66 20 74 cessors. The newer members of t 00001000 68 65 20 66 61 6D 69 6C 79 20 61 72 65 20 63 61 70 61 62 6C 65 20 6F 66 20 65 78 65 63 75 74 69 he family are capable of executi 00001020 6E 67 20 61 6E 79 20 62 69 6E 61 72 69 65 73 20 63 72 65 61 74 65 64 20 66 6F 72 20 6D 65 6D 62 ng any binaries created for memb 00001040 65 72 73 20 6F 66 20 70 72 65 76 69 6F 75 73 20 67 65 6E 65 72 61 74 69 6F 6E 73 2E 20 46 6F 72 ers of previous generations. For 00001060 20 65 78 61 6D 70 6C 65 2C 20 61 6E 79 20 65 78 69 73 74 69 6E 67 20 38 30 38 36 2F 38 30 38 38 example, any existing 8086/8088 00001080 2C 20 38 30 32 38 36 2C 20 49 6E 74 65 6C 33 38 36 20 28 44 58 20 6F 72 20 53 58 29 2C 20 61 6E , 80286, Intel386 (DX or SX), an 000010A0 64 20 49 6E 74 65 6C 34 38 36 20 61 70 70 6C 69 63 61 74 69 6F 6E 73 20 77 69 6C 6C 20 62 65 20 d Intel486 applications will be 000010C0 61 62 6C 65 20 74 6F 20 65 78 65 63 75 74 65 20 6F 6E 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 able to execute on the Pentium p 000010E0 72 6F 63 65 73 73 6F 72 20 77 69 74 68 6F 75 74 20 61 6E 79 20 6D 6F 64 69 66 69 63 61 74 69 6F rocessor without any modificatio 00001100 6E 20 6F 72 20 72 65 63 6F 6D 70 69 6C 61 74 69 6F 6E 2E 20 48 6F 77 65 76 65 72 2C 20 74 68 65 n or recompilation. However, the 00001120 72 65 20 61 72 65 20 63 65 72 74 61 69 6E 20 63 6F 64 65 20 6F 70 74 69 6D 69 7A 61 74 69 6F 6E re are certain code optimization 00001140 0D 0A 74 65 63 68 6E 69 71 75 65 73 20 77 68 69 63 68 20 77 69 6C 6C 20 6D 61 6B 65 20 61 70 70 ♪◙techniques which will make app 00001160 6C 69 63 61 74 69 6F 6E 73 20 65 78 65 63 75 74 65 20 66 61 73 74 65 72 20 6F 6E 20 61 20 73 70 lications execute faster on a sp 00001180 65 63 69 66 69 63 20 6D 65 6D 62 65 72 20 6F 66 20 74 68 65 20 66 61 6D 69 6C 79 20 77 69 74 68 ecific member of the family with 000011A0 0D 0A 6C 69 74 74 6C 65 20 6F 72 20 6E 6F 20 69 6D 70 61 63 74 20 6F 6E 20 74 68 65 20 70 65 72 ♪◙little or no impact on the per 000011C0 66 6F 72 6D 61 6E 63 65 20 6F 66 20 6F 74 68 65 72 20 6D 65 6D 62 65 72 73 2E 20 4D 6F 73 74 20 formance of other members. Most 000011E0 6F 66 20 74 68 65 73 65 20 6F 70 74 69 6D 69 7A 61 74 69 6F 6E 73 20 64 65 61 6C 20 77 69 74 68 of these optimizations deal with 00001200 0D 0A 69 6E 73 74 72 75 63 74 69 6F 6E 20 73 65 71 75 65 6E 63 65 20 73 65 6C 65 63 74 69 6F 6E ♪◙instruction sequence selection 00001220 20 61 6E 64 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 72 65 6F 72 64 65 72 69 6E 67 20 74 6F 20 63 and instruction reordering to c 00001240 6F 6D 70 6C 65 6D 65 6E 74 20 74 68 65 20 70 72 6F 63 65 73 73 6F 72 0D 0A 6D 69 63 72 6F 20 61 omplement the processor♪◙micro a 00001260 72 63 68 69 74 65 63 74 75 72 65 20 2E 0D 0A 0D 0A 54 68 65 20 69 6E 74 65 6E 74 20 6F 66 20 74 rchitecture .♪◙♪◙The intent of t 00001280 68 69 73 20 64 6F 63 75 6D 65 6E 74 20 69 73 20 74 6F 20 64 65 73 63 72 69 62 65 20 74 68 65 20 his document is to describe the 000012A0 69 6D 70 6C 65 6D 65 6E 74 61 74 69 6F 6E 20 64 69 66 66 65 72 65 6E 63 65 73 20 6F 66 20 74 68 implementation differences of th 000012C0 65 20 70 72 6F 63 65 73 73 6F 72 20 6D 65 6D 62 65 72 73 0D 0A 61 6E 64 20 74 68 65 20 6F 70 74 e processor members♪◙and the opt 000012E0 69 6D 69 7A 61 74 69 6F 6E 20 73 74 72 61 74 65 67 79 20 74 68 61 74 20 67 69 76 65 73 20 74 68 imization strategy that gives th 00001300 65 20 62 65 73 74 20 70 65 72 66 6F 72 6D 61 6E 63 65 20 66 6F 72 20 61 6C 6C 20 6D 65 6D 62 65 e best performance for all membe 00001320 72 73 20 6F 66 20 74 68 65 20 66 61 6D 69 6C 79 2E 0D 0A 0D 0A 32 2E 20 4F 76 65 72 76 69 65 77 rs of the family.♪◙♪◙2. Overview 00001340 20 6F 66 20 49 6E 74 65 6C 33 38 36 2C 20 49 6E 74 65 6C 34 38 36 2C 20 61 6E 64 20 50 65 6E 74 of Intel386, Intel486, and Pent 00001360 69 75 6D 20 50 72 6F 63 65 73 73 6F 72 73 0D 0A 0D 0A 32 2E 31 20 54 68 65 20 49 6E 74 65 6C 33 ium Processors♪◙♪◙2.1 The Intel3 00001380 38 36 20 50 72 6F 63 65 73 73 6F 72 0D 0A 0D 0A 54 68 65 20 49 6E 74 65 6C 33 38 36 20 70 72 6F 86 Processor♪◙♪◙The Intel386 pro 000013A0 63 65 73 73 6F 72 20 69 73 20 74 68 65 20 66 69 72 73 74 20 69 6D 70 6C 65 6D 65 6E 74 61 74 69 cessor is the first implementati 000013C0 6F 6E 20 6F 66 20 74 68 65 20 33 32 2D 62 69 74 20 49 6E 74 65 6C 33 38 36 20 61 72 63 68 69 74 on of the 32-bit Intel386 archit 000013E0 65 63 74 75 72 65 2E 20 49 74 20 69 6E 63 6C 75 64 65 73 20 66 75 6C 6C 0D 0A 33 32 2D 62 69 74 ecture. It includes full♪◙32-bit 00001400 20 64 61 74 61 20 70 61 74 68 73 2C 20 72 69 63 68 20 33 32 2D 62 69 74 20 61 64 64 72 65 73 73 data paths, rich 32-bit address 00001420 69 6E 67 20 6D 6F 64 65 73 20 61 6E 64 20 6F 6E 2D 63 68 69 70 20 6D 65 6D 6F 72 79 20 6D 61 6E ing modes and on-chip memory man 00001440 61 67 65 6D 65 6E 74 2E 0D 0A 0D 0A 32 2E 31 2E 31 2E 20 49 6E 73 74 72 75 63 74 69 6F 6E 20 50 agement.♪◙♪◙2.1.1. Instruction P 00001460 72 65 66 65 74 63 68 65 72 0D 0A 0D 0A 54 68 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 70 72 65 refetcher♪◙♪◙The instruction pre 00001480 66 65 74 63 68 65 72 20 70 72 65 66 65 74 63 68 65 73 20 74 68 65 20 69 6E 73 74 72 75 63 74 69 fetcher prefetches the instructi 000014A0 6F 6E 20 73 74 72 65 61 6D 20 66 72 6F 6D 20 65 78 74 65 72 6E 61 6C 20 6D 65 6D 6F 72 79 20 61 on stream from external memory a 000014C0 6E 64 20 74 68 65 20 70 72 65 66 65 74 63 68 65 64 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 61 nd the prefetched instructions a 000014E0 72 65 20 6B 65 70 74 20 69 6E 20 69 74 73 20 66 6F 75 72 2D 64 65 65 70 2C 20 66 6F 75 72 2D 62 re kept in its four-deep, four-b 00001500 79 74 65 2D 77 69 64 65 20 70 72 65 66 65 74 63 68 20 62 75 66 66 65 72 73 2E 20 54 68 65 20 69 yte-wide prefetch buffers. The i 00001520 6E 73 74 72 75 63 74 69 6F 6E 20 64 65 63 6F 64 65 72 20 6F 70 65 72 61 74 65 73 20 6F 6E 20 74 nstruction decoder operates on t 00001540 68 65 20 63 6F 64 65 20 73 74 72 65 61 6D 20 66 65 64 20 74 6F 20 69 74 20 74 68 72 6F 75 67 68 he code stream fed to it through 00001560 20 74 68 65 20 70 72 65 66 65 74 63 68 20 62 75 66 66 65 72 73 2E 0D 0A 0D 0A 32 2E 31 2E 32 2E the prefetch buffers.♪◙♪◙2.1.2. 00001580 20 49 6E 73 74 72 75 63 74 69 6F 6E 20 44 65 63 6F 64 65 72 0D 0A 0D 0A 54 68 65 20 69 6E 73 74 Instruction Decoder♪◙♪◙The inst 000015A0 72 75 63 74 69 6F 6E 20 64 65 63 6F 64 65 72 20 70 6C 61 63 65 73 20 74 68 65 20 64 65 63 6F 64 ruction decoder places the decod 000015C0 65 64 20 69 6E 66 6F 72 6D 61 74 69 6F 6E 20 69 6E 20 61 20 74 68 72 65 65 2D 64 65 65 70 20 46 ed information in a three-deep F 000015E0 49 46 4F 2E 20 49 74 20 69 73 20 64 65 63 6F 75 70 6C 65 64 20 66 72 6F 6D 20 62 6F 74 68 20 74 IFO. It is decoupled from both t 00001600 68 65 20 70 72 65 66 65 74 63 68 65 72 20 61 6E 64 20 74 68 65 20 65 78 65 63 75 74 69 6F 6E 20 he prefetcher and the execution 00001620 63 6F 72 65 20 61 6E 64 20 68 61 73 20 73 65 70 61 72 61 74 65 20 70 72 6F 74 6F 63 6F 6C 73 20 core and has separate protocols 00001640 77 69 74 68 20 65 61 63 68 2E 0D 0A 0D 0A 32 2E 31 2E 33 2E 20 45 78 65 63 75 74 69 6F 6E 20 43 with each.♪◙♪◙2.1.3. Execution C 00001660 6F 72 65 0D 0A 0D 0A 54 68 65 20 63 6F 72 65 20 65 6E 67 69 6E 65 20 65 78 65 63 75 74 65 73 20 ore♪◙♪◙The core engine executes 00001680 74 68 65 20 69 6E 63 6F 6D 69 6E 67 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 6F 6E 65 20 61 74 the incoming instructions one at 000016A0 20 61 20 74 69 6D 65 2C 20 62 75 74 20 66 6F 72 20 63 65 72 74 61 69 6E 20 63 61 73 65 73 2C 20 a time, but for certain cases, 000016C0 69 74 20 61 6C 6C 6F 77 73 20 6F 76 65 72 6C 61 70 70 69 6E 67 20 74 68 65 20 6C 61 73 74 20 65 it allows overlapping the last e 000016E0 78 65 63 75 74 69 6F 6E 20 63 79 63 6C 65 20 6F 66 20 74 68 65 20 63 75 72 72 65 6E 74 20 69 6E xecution cycle of the current in 00001700 73 74 72 75 63 74 69 6F 6E 20 77 69 74 68 20 74 68 65 20 65 66 66 65 63 74 69 76 65 20 61 64 64 struction with the effective add 00001720 72 65 73 73 20 63 61 6C 63 75 6C 61 74 69 6F 6E 20 6F 66 20 74 68 65 20 6E 65 78 74 20 69 6E 73 ress calculation of the next ins 00001740 74 72 75 63 74 69 6F 6E 27 73 20 6D 65 6D 6F 72 79 20 72 65 66 65 72 65 6E 63 65 2E 0D 0A 0D 0A truction's memory reference.♪◙♪◙ 00001760 46 72 6F 6D 20 74 68 65 20 63 6F 6D 70 69 6C 65 72 20 77 72 69 74 65 72 27 73 20 70 6F 69 6E 74 From the compiler writer's point 00001780 20 6F 66 20 76 69 65 77 2C 20 74 68 65 20 64 65 63 6F 75 70 6C 65 64 20 70 72 65 66 65 74 63 68 of view, the decoupled prefetch 000017A0 2F 64 65 63 6F 64 65 2F 65 78 65 63 75 74 69 6F 6E 20 73 74 61 67 65 73 20 61 6E 64 20 74 68 65 /decode/execution stages and the 000017C0 20 73 65 71 75 65 6E 74 69 61 6C 20 6E 61 74 75 72 65 20 6F 66 20 74 68 65 20 63 6F 72 65 20 65 sequential nature of the core e 000017E0 6E 67 69 6E 65 20 68 61 73 20 70 6C 61 63 65 64 20 66 65 77 20 72 65 71 75 69 72 65 6D 65 6E 74 ngine has placed few requirement 00001800 73 20 66 6F 72 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 73 63 68 65 64 75 6C 69 6E 67 2E 20 20 41 s for instruction scheduling. A 00001820 76 6F 69 64 69 6E 67 20 74 68 65 20 75 73 65 20 6F 66 20 61 6E 20 69 6E 64 65 78 20 69 6E 20 74 voiding the use of an index in t 00001840 68 65 20 65 66 66 65 63 74 69 76 65 20 61 64 64 72 65 73 73 20 77 69 6C 6C 20 73 61 76 65 20 6F he effective address will save o 00001860 6E 65 20 65 78 74 72 61 20 63 6C 6F 63 6B 2E 20 41 20 63 61 72 65 66 75 6C 20 63 68 6F 69 63 65 ne extra clock. A careful choice 00001880 20 6F 66 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 74 6F 20 6D 69 6E 69 6D 69 7A 65 20 74 68 65 of instructions to minimize the 000018A0 20 65 78 65 63 75 74 69 6F 6E 20 63 6C 6F 63 6B 20 63 6F 75 6E 74 73 20 69 73 20 74 68 65 20 62 execution clock counts is the b 000018C0 65 73 74 20 6F 70 74 69 6D 69 7A 61 74 69 6F 6E 20 61 70 70 72 6F 61 63 68 2E 0D 0A 0D 0A 32 2E est optimization approach.♪◙♪◙2. 000018E0 32 20 54 68 65 20 49 6E 74 65 6C 34 38 36 20 50 72 6F 63 65 73 73 6F 72 0D 0A 0D 0A 54 68 65 20 2 The Intel486 Processor♪◙♪◙The 00001900 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 20 68 61 73 20 61 20 66 75 6C 6C 20 62 6C Intel486 processor has a full bl 00001920 6F 77 6E 20 69 6E 74 65 67 65 72 20 70 69 70 65 6C 69 6E 65 20 64 65 6C 69 76 65 72 69 6E 67 20 own integer pipeline delivering 00001940 61 20 70 65 61 6B 20 74 68 72 6F 75 67 68 70 75 74 20 6F 66 20 6F 6E 65 20 69 6E 73 74 72 75 63 a peak throughput of one instruc 00001960 74 69 6F 6E 20 70 65 72 20 63 6C 6F 63 6B 2E 20 49 74 20 68 61 73 20 69 6E 74 65 67 72 61 74 65 tion per clock. It has integrate 00001980 64 20 74 68 65 20 66 69 72 73 74 20 6C 65 76 65 6C 20 63 61 63 68 65 20 61 6E 64 20 74 68 65 20 d the first level cache and the 000019A0 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 75 6E 69 74 20 6F 6E 20 63 68 69 70 2C 20 61 6E 64 floating-point unit on chip, and 000019C0 20 69 74 20 68 61 73 20 74 68 65 20 73 61 6D 65 20 6F 6E 2D 63 68 69 70 20 6D 65 6D 6F 72 79 20 it has the same on-chip memory 000019E0 6D 61 6E 61 67 65 6D 65 6E 74 20 63 61 70 61 62 69 6C 69 74 69 65 73 20 61 73 20 74 68 65 20 49 management capabilities as the I 00001A00 6E 74 65 6C 33 38 36 20 70 72 6F 63 65 73 73 6F 72 2E 0D 0A 0D 0A 0C 0D 0A 32 2E 32 2E 31 2E 20 ntel386 processor.♪◙♪◙♀♪◙2.2.1. 00001A20 49 6E 74 65 67 65 72 20 50 69 70 65 6C 69 6E 65 0D 0A 0D 0A 54 68 65 20 49 6E 74 65 6C 34 38 36 Integer Pipeline♪◙♪◙The Intel486 00001A40 20 68 61 73 20 61 20 66 69 76 65 2D 73 74 61 67 65 20 69 6E 74 65 67 65 72 20 70 69 70 65 6C 69 has a five-stage integer pipeli 00001A60 6E 65 20 63 61 70 61 62 6C 65 20 6F 66 20 70 72 6F 63 65 73 73 69 6E 67 20 6F 6E 65 20 69 6E 73 ne capable of processing one ins 00001A80 74 72 75 63 74 69 6F 6E 20 70 65 72 20 63 6C 6F 63 6B 2E 0D 0A 54 68 65 20 66 69 76 65 20 70 69 truction per clock.♪◙The five pi 00001AA0 70 65 6C 69 6E 65 20 73 74 61 67 65 73 20 61 72 65 3A 0D 0A 0D 0A 61 2E 20 50 72 65 66 65 74 63 peline stages are:♪◙♪◙a. Prefetc 00001AC0 68 2C 20 28 50 46 29 20 2D 20 77 68 65 72 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 61 72 65 h, (PF) - where instructions are 00001AE0 20 66 65 74 63 68 65 64 20 66 72 6F 6D 20 74 68 65 20 63 61 63 68 65 20 61 6E 64 20 70 6C 61 63 fetched from the cache and plac 00001B00 65 64 20 69 6E 20 6F 6E 65 20 6F 66 20 74 77 6F 20 31 36 2D 62 79 74 65 20 62 75 66 66 65 72 73 ed in one of two 16-byte buffers 00001B20 2E 0D 0A 0D 0A 62 2E 20 44 65 63 6F 64 65 20 28 44 31 29 20 2D 20 77 68 65 72 65 20 69 6E 63 6F .♪◙♪◙b. Decode (D1) - where inco 00001B40 6D 69 6E 67 20 63 6F 64 65 20 73 74 72 65 61 6D 20 69 73 20 62 65 69 6E 67 20 64 65 63 6F 64 65 ming code stream is being decode 00001B60 64 2E 20 50 72 65 66 69 78 65 64 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 73 74 61 79 20 69 6E d. Prefixed instructions stay in 00001B80 20 44 31 20 66 6F 72 20 74 77 6F 20 63 6C 6F 63 6B 73 2E 0D 0A 0D 0A 63 2E 20 41 64 64 72 65 73 D1 for two clocks.♪◙♪◙c. Addres 00001BA0 73 20 47 65 6E 65 72 61 74 69 6F 6E 20 28 44 32 29 20 2D 20 77 68 65 72 65 20 65 66 66 65 63 74 s Generation (D2) - where effect 00001BC0 69 76 65 20 61 64 64 72 65 73 73 20 61 6E 64 20 6C 69 6E 65 61 72 20 61 64 64 72 65 73 73 20 61 ive address and linear address a 00001BE0 72 65 20 63 61 6C 63 75 6C 61 74 65 64 20 69 6E 20 70 61 72 61 6C 6C 65 6C 2E 20 54 68 65 20 61 re calculated in parallel. The a 00001C00 64 64 72 65 73 73 20 67 65 6E 65 72 61 74 69 6F 6E 20 63 61 6E 20 75 73 75 61 6C 6C 79 20 62 65 ddress generation can usually be 00001C20 20 63 6F 6D 70 6C 65 74 65 64 20 69 6E 20 6F 6E 65 20 63 79 63 6C 65 20 65 78 63 65 70 74 20 69 completed in one cycle except i 00001C40 6E 20 63 61 73 65 73 20 77 68 65 72 65 20 74 68 65 20 69 6E 64 65 78 65 64 20 61 64 64 72 65 73 n cases where the indexed addres 00001C60 73 69 6E 67 20 6D 6F 64 65 20 69 73 20 75 73 65 64 2E 20 49 66 20 74 68 65 20 69 6E 64 65 78 20 sing mode is used. If the index 00001C80 69 73 20 75 73 65 64 2C 20 74 68 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 73 74 61 79 73 20 69 is used, the instruction stays i 00001CA0 6E 20 44 32 20 66 6F 72 20 74 77 6F 20 63 6C 6F 63 6B 73 2E 0D 0A 0D 0A 64 2E 20 45 78 65 63 75 n D2 for two clocks.♪◙♪◙d. Execu 00001CC0 74 69 6F 6E 20 28 45 29 20 2D 20 77 68 65 72 65 20 74 68 65 20 6D 61 63 68 69 6E 65 20 6F 70 65 tion (E) - where the machine ope 00001CE0 72 61 74 69 6F 6E 73 20 61 72 65 20 70 65 72 66 6F 72 6D 65 64 2E 20 53 69 6D 70 6C 65 20 69 6E rations are performed. Simple in 00001D00 73 74 72 75 63 74 69 6F 6E 73 20 28 74 68 6F 73 65 20 77 69 74 68 20 6F 6E 65 20 6D 61 63 68 69 structions (those with one machi 00001D20 6E 65 20 6F 70 65 72 61 74 69 6F 6E 29 20 74 61 6B 65 20 6F 6E 65 20 63 79 63 6C 65 20 74 6F 20 ne operation) take one cycle to 00001D40 65 78 65 63 75 74 65 20 67 69 76 69 6E 67 20 61 20 6D 61 78 69 6D 75 6D 20 74 68 72 6F 75 67 68 execute giving a maximum through 00001D60 70 75 74 20 6F 66 20 6F 6E 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 70 65 72 20 63 6C 6F 63 6B put of one instruction per clock 00001D80 2E 20 54 68 65 20 6D 6F 72 65 20 63 6F 6D 70 6C 65 78 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 . The more complex instructions 00001DA0 74 61 6B 65 20 6D 75 6C 74 69 70 6C 65 20 65 78 65 63 75 74 69 6F 6E 20 63 79 63 6C 65 73 2E 0D take multiple execution cycles.♪ 00001DC0 0A 0D 0A 65 2E 20 57 72 69 74 65 62 61 63 6B 20 28 57 42 29 20 2D 20 77 68 65 72 65 20 74 68 65 ◙♪◙e. Writeback (WB) - where the 00001DE0 20 6E 65 65 64 65 64 20 72 65 67 69 73 74 65 72 20 75 70 64 61 74 65 20 6F 63 63 75 72 73 2E 0D needed register update occurs.♪ 00001E00 0A 0D 0A 41 20 74 61 6B 65 6E 20 62 72 61 6E 63 68 20 62 72 65 61 6B 73 20 74 68 65 20 70 69 70 ◙♪◙A taken branch breaks the pip 00001E20 65 6C 69 6E 65 20 73 74 72 65 61 6D 20 61 6E 64 20 63 61 75 73 65 73 20 61 20 74 77 6F 2D 63 6C eline stream and causes a two-cl 00001E40 6F 63 6B 20 70 65 6E 61 6C 74 79 2C 20 77 68 65 72 65 61 73 20 74 68 65 20 70 69 70 65 6C 69 6E ock penalty, whereas the pipelin 00001E60 65 20 73 74 72 65 61 6D 20 69 73 20 75 6E 61 66 66 65 63 74 65 64 20 62 79 20 61 20 6E 6F 74 2D e stream is unaffected by a not- 00001E80 74 61 6B 65 6E 20 62 72 61 6E 63 68 2E 0D 0A 0D 0A 32 2E 32 2E 32 2E 20 4F 6E 2D 43 68 69 70 20 taken branch.♪◙♪◙2.2.2. On-Chip 00001EA0 43 61 63 68 65 0D 0A 0D 0A 54 68 65 20 6F 6E 2D 63 68 69 70 20 63 61 63 68 65 20 69 73 20 61 20 Cache♪◙♪◙The on-chip cache is a 00001EC0 63 6F 6D 62 69 6E 65 64 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 61 6E 64 20 64 61 74 61 20 63 61 combined instruction and data ca 00001EE0 63 68 65 2E 20 49 74 20 69 73 20 38 2D 4B 62 79 74 65 73 20 69 6E 20 73 69 7A 65 2C 20 66 6F 75 che. It is 8-Kbytes in size, fou 00001F00 72 2D 77 61 79 20 73 65 74 20 61 73 73 6F 63 69 61 74 69 76 65 20 77 69 74 68 20 61 20 31 36 2D r-way set associative with a 16- 00001F20 62 79 74 65 20 6C 69 6E 65 20 73 69 7A 65 20 61 6E 64 20 70 73 65 75 64 6F 2D 4C 52 55 20 72 65 byte line size and pseudo-LRU re 00001F40 70 6C 61 63 65 6D 65 6E 74 20 61 6C 67 6F 72 69 74 68 6D 2E 20 41 6C 6C 20 64 61 74 61 20 72 65 placement algorithm. All data re 00001F60 66 65 72 65 6E 63 65 73 20 68 61 76 65 20 70 72 69 6F 72 69 74 79 20 61 63 63 65 73 73 20 74 6F ferences have priority access to 00001F80 20 74 68 65 20 63 61 63 68 65 20 6F 76 65 72 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 70 72 65 66 the cache over instruction pref 00001FA0 65 74 63 68 20 63 79 63 6C 65 73 2E 0D 0A 0D 0A 32 2E 32 2E 33 2E 20 4F 6E 2D 43 68 69 70 20 46 etch cycles.♪◙♪◙2.2.3. On-Chip F 00001FC0 6C 6F 61 74 69 6E 67 2D 50 6F 69 6E 74 20 55 6E 69 74 0D 0A 0D 0A 54 68 65 20 6F 6E 2D 63 68 69 loating-Point Unit♪◙♪◙The on-chi 00001FE0 70 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 75 6E 69 74 20 75 74 69 6C 69 7A 65 73 20 74 p floating-point unit utilizes t 00002000 68 65 20 69 6E 74 65 67 65 72 20 70 69 70 65 6C 69 6E 65 20 66 6F 72 20 65 61 72 6C 79 20 64 61 he integer pipeline for early da 00002020 74 61 20 61 63 63 65 73 73 2E 20 54 68 65 20 62 75 73 20 73 74 72 75 63 74 75 72 65 20 61 6C 6C ta access. The bus structure all 00002040 6F 77 73 20 36 34 2D 62 69 74 20 64 61 74 61 20 74 6F 20 62 65 20 74 72 61 6E 73 66 65 72 72 65 ows 64-bit data to be transferre 00002060 64 20 62 65 74 77 65 65 6E 20 74 68 65 20 63 61 63 68 65 20 61 6E 64 20 74 68 65 20 66 6C 6F 61 d between the cache and the floa 00002080 74 69 6E 67 20 70 6F 69 6E 74 20 68 61 72 64 77 61 72 65 20 69 6E 20 6F 6E 65 20 63 6C 6F 63 6B ting point hardware in one clock 000020A0 2E 20 54 68 65 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 64 65 73 69 67 6E 20 61 6C 73 6F . The floating-point design also 000020C0 20 61 6C 6C 6F 77 73 20 6F 76 65 72 6C 61 70 70 69 6E 67 20 74 68 65 20 66 6C 6F 61 74 69 6E 67 allows overlapping the floating 000020E0 2D 70 6F 69 6E 74 20 6F 70 65 72 61 74 69 6F 6E 73 20 77 69 74 68 20 69 6E 74 65 67 65 72 20 6F -point operations with integer o 00002100 70 65 72 61 74 69 6F 6E 73 2E 0D 0A 0D 0A 54 68 65 20 65 78 65 63 75 74 69 6F 6E 20 63 6F 72 65 perations.♪◙♪◙The execution core 00002120 20 6F 66 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 20 68 61 73 20 62 of the Intel486 processor has b 00002140 65 65 6E 20 61 72 63 68 69 74 65 63 74 65 64 20 74 6F 20 6D 61 78 69 6D 69 7A 65 20 74 68 65 20 een architected to maximize the 00002160 74 68 72 6F 75 67 68 70 75 74 20 6F 66 20 61 20 63 6C 61 73 73 20 6F 66 20 22 66 72 65 71 75 65 throughput of a class of "freque 00002180 6E 74 6C 79 20 75 73 65 64 22 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 2E 20 48 65 6E 63 65 2C 20 ntly used" instructions. Hence, 000021A0 63 61 72 65 66 75 6C 20 73 65 6C 65 63 74 69 6F 6E 20 6F 66 20 61 6E 20 69 6E 73 74 72 75 63 74 careful selection of an instruct 000021C0 69 6F 6E 20 73 65 71 75 65 6E 63 65 20 74 6F 20 70 65 72 66 6F 72 6D 20 61 20 67 69 76 65 6E 20 ion sequence to perform a given 000021E0 74 61 73 6B 20 72 65 73 75 6C 74 73 20 69 6E 20 66 61 73 74 65 72 20 65 78 65 63 75 74 69 6F 6E task results in faster execution 00002200 20 74 69 6D 65 2E 20 41 6C 73 6F 2C 20 63 6F 64 65 20 73 63 68 65 64 75 6C 69 6E 67 20 74 6F 20 time. Also, code scheduling to 00002220 61 76 6F 69 64 20 70 69 70 65 6C 69 6E 65 20 73 74 61 6C 6C 73 20 68 65 6C 70 73 20 74 6F 20 62 avoid pipeline stalls helps to b 00002240 6F 6F 73 74 20 61 70 70 6C 69 63 61 74 69 6F 6E 20 70 65 72 66 6F 72 6D 61 6E 63 65 2E 20 4D 6F oost application performance. Mo 00002260 73 74 20 6F 66 20 74 68 65 20 6F 70 74 69 6D 69 7A 61 74 69 6F 6E 73 20 74 61 72 67 65 74 65 64 st of the optimizations targeted 00002280 20 74 6F 20 74 68 65 20 49 6E 74 65 6C 34 38 36 13 53 59 4D 42 4F 4C 20 32 32 38 20 5C 66 20 22 to the Intel486‼SYMBOL 228 \f " 000022A0 53 79 6D 62 6F 6C 22 15 20 70 72 6F 63 65 73 73 6F 72 20 64 6F 20 6E 6F 74 20 68 61 76 65 20 6E Symbol"§ processor do not have n 000022C0 65 67 61 74 69 76 65 20 65 66 66 65 63 74 73 20 6F 6E 20 49 6E 74 65 6C 33 38 36 13 53 59 4D 42 egative effects on Intel386‼SYMB 000022E0 4F 4C 20 32 32 38 20 5C 66 20 22 53 79 6D 62 6F 6C 22 15 20 70 72 6F 63 65 73 73 6F 72 2E 0D 0A OL 228 \f "Symbol"§ processor.♪◙ 00002300 0D 0A 32 2E 33 20 54 68 65 20 50 65 6E 74 69 75 6D 20 50 72 6F 63 65 73 73 6F 72 0D 0A 0D 0A 54 ♪◙2.3 The Pentium Processor♪◙♪◙T 00002320 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 20 69 73 20 61 6E 20 61 64 76 61 6E he Pentium processor is an advan 00002340 63 65 64 20 73 75 70 65 72 73 63 61 6C 61 72 20 70 72 6F 63 65 73 73 6F 72 2E 20 20 49 74 20 69 ced superscalar processor. It i 00002360 73 20 62 75 69 6C 74 20 61 72 6F 75 6E 64 20 74 77 6F 20 67 65 6E 65 72 61 6C 20 70 75 72 70 6F s built around two general purpo 00002380 73 65 20 69 6E 74 65 67 65 72 20 70 69 70 65 6C 69 6E 65 73 20 61 6E 64 20 61 20 70 69 70 65 6C se integer pipelines and a pipel 000023A0 69 6E 65 64 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 75 6E 69 74 2E 20 54 68 65 20 50 65 ined floating-point unit. The Pe 000023C0 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 20 63 61 6E 20 65 78 65 63 75 74 65 20 74 77 6F 20 ntium processor can execute two 000023E0 69 6E 74 65 67 65 72 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 73 69 6D 75 6C 74 61 6E 65 6F 75 integer instructions simultaneou 00002400 73 6C 79 2E 20 41 20 73 6F 66 74 77 61 72 65 2D 74 72 61 6E 73 70 61 72 65 6E 74 20 64 79 6E 61 sly. A software-transparent dyna 00002420 6D 69 63 20 62 72 61 6E 63 68 2D 70 72 65 64 69 63 74 69 6F 6E 20 6D 65 63 68 61 6E 69 73 6D 20 mic branch-prediction mechanism 00002440 6D 69 6E 69 6D 69 7A 65 73 20 70 69 70 65 6C 69 6E 65 20 73 74 61 6C 6C 73 20 64 75 65 20 74 6F minimizes pipeline stalls due to 00002460 20 62 72 61 6E 63 68 65 73 2E 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 32 2E 33 2E 31 2E 20 49 6E 74 branches.♪◙♪◙♪◙♪◙♪◙♪◙2.3.1. Int 00002480 65 67 65 72 20 50 69 70 65 6C 69 6E 65 73 0D 0A 0D 0A 54 68 65 20 50 65 6E 74 69 75 6D 20 70 72 eger Pipelines♪◙♪◙The Pentium pr 000024A0 6F 63 65 73 73 6F 72 20 68 61 73 20 74 77 6F 20 70 61 72 61 6C 6C 65 6C 20 69 6E 74 65 67 65 72 ocessor has two parallel integer 000024C0 20 70 69 70 65 6C 69 6E 65 73 2C 20 74 68 65 20 6D 61 69 6E 20 70 69 70 65 20 28 55 29 20 77 68 pipelines, the main pipe (U) wh 000024E0 69 63 68 20 69 73 20 61 6E 20 65 6E 68 61 6E 63 65 64 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 ich is an enhanced Intel486 proc 00002500 65 73 73 6F 72 20 70 69 70 65 20 61 6E 64 20 74 68 65 20 73 65 63 6F 6E 64 61 72 79 20 70 69 70 essor pipe and the secondary pip 00002520 65 20 28 56 29 20 77 68 69 63 68 20 69 73 20 73 69 6D 69 6C 61 72 20 74 6F 20 74 68 65 20 6D 61 e (V) which is similar to the ma 00002540 69 6E 20 6F 6E 65 20 62 75 74 20 68 61 73 20 73 6F 6D 65 20 6C 69 6D 69 74 61 74 69 6F 6E 73 20 in one but has some limitations 00002560 6F 6E 20 74 68 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 69 74 20 63 61 6E 20 65 78 65 63 75 on the instructions it can execu 00002580 74 65 2E 20 54 68 65 20 6C 69 6D 69 74 61 74 69 6F 6E 73 20 77 69 6C 6C 20 62 65 20 64 65 73 63 te. The limitations will be desc 000025A0 72 69 62 65 64 20 69 6E 20 6D 6F 72 65 0D 0A 64 65 74 61 69 6C 20 69 6E 20 6C 61 74 65 72 20 73 ribed in more♪◙detail in later s 000025C0 65 63 74 69 6F 6E 73 2E 0D 0A 0D 0A 54 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F ections.♪◙♪◙The Pentium processo 000025E0 72 20 63 61 6E 20 69 73 73 75 65 20 74 77 6F 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 65 76 65 r can issue two instructions eve 00002600 72 79 20 63 79 63 6C 65 2E 20 44 75 72 69 6E 67 20 65 78 65 63 75 74 69 6F 6E 2C 20 74 68 65 20 ry cycle. During execution, the 00002620 6E 65 78 74 20 74 77 6F 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 61 72 65 20 63 68 65 63 6B 65 next two instructions are checke 00002640 64 2C 20 61 6E 64 20 69 66 20 70 6F 73 73 69 62 6C 65 2C 20 74 68 65 79 20 61 72 65 20 69 73 73 d, and if possible, they are iss 00002660 75 65 64 20 73 75 63 68 20 74 68 61 74 20 74 68 65 20 66 69 72 73 74 20 6F 6E 65 20 65 78 65 63 ued such that the first one exec 00002680 75 74 65 73 20 69 6E 20 74 68 65 20 55 20 70 69 70 65 2C 20 61 6E 64 20 74 68 65 20 73 65 63 6F utes in the U pipe, and the seco 000026A0 6E 64 20 69 6E 20 74 68 65 20 56 20 20 70 69 70 65 2E 20 28 49 66 20 69 74 20 69 73 20 6E 6F 74 nd in the V pipe. (If it is not 000026C0 20 70 6F 73 73 69 62 6C 65 20 74 6F 20 69 73 73 75 65 20 74 77 6F 20 69 6E 73 74 72 75 63 74 69 possible to issue two instructi 000026E0 6F 6E 73 2C 20 74 68 65 6E 20 74 68 65 20 6E 65 78 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 69 ons, then the next instruction i 00002700 73 20 69 73 73 75 65 64 20 74 6F 20 74 68 65 20 55 20 70 69 70 65 20 61 6E 64 20 6E 6F 20 69 6E s issued to the U pipe and no in 00002720 73 74 72 75 63 74 69 6F 6E 20 69 73 20 69 73 73 75 65 64 20 74 6F 20 74 68 65 20 56 20 20 70 69 struction is issued to the V pi 00002740 70 65 2E 29 0D 0A 0D 0A 57 68 65 6E 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 65 78 65 63 75 74 pe.)♪◙♪◙When instructions execut 00002760 65 20 69 6E 20 74 68 65 20 74 77 6F 20 70 69 70 65 73 2C 20 74 68 65 69 72 20 62 65 68 61 76 69 e in the two pipes, their behavi 00002780 6F 72 20 69 73 20 65 78 61 63 74 6C 79 20 74 68 65 20 73 61 6D 65 20 61 73 20 69 66 20 74 68 65 or is exactly the same as if the 000027A0 79 20 77 65 72 65 20 65 78 65 63 75 74 65 64 20 73 65 71 75 65 6E 74 69 61 6C 6C 79 2E 20 57 68 y were executed sequentially. Wh 000027C0 65 6E 20 61 20 73 74 61 6C 6C 20 6F 63 63 75 72 73 2C 20 73 75 63 63 65 73 73 69 76 65 20 69 6E en a stall occurs, successive in 000027E0 73 74 72 75 63 74 69 6F 6E 73 20 61 72 65 20 6E 6F 74 20 61 6C 6C 6F 77 65 64 20 74 6F 20 70 61 structions are not allowed to pa 00002800 73 73 20 74 68 65 20 73 74 61 6C 6C 65 64 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 69 6E 20 65 69 ss the stalled instruction in ei 00002820 74 68 65 72 20 70 69 70 65 2E 20 49 6E 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 ther pipe. In the Pentium proces 00002840 73 6F 72 27 73 20 70 69 70 65 6C 69 6E 65 73 2C 20 74 68 65 20 44 32 20 73 74 61 67 65 20 63 61 sor's pipelines, the D2 stage ca 00002860 6E 20 70 65 72 66 6F 72 6D 20 61 20 6D 75 6C 74 69 77 61 79 20 61 64 64 2C 20 73 6F 20 74 68 65 n perform a multiway add, so the 00002880 72 65 20 69 73 20 6E 6F 74 20 61 20 6F 6E 65 2D 63 6C 6F 63 6B 20 69 6E 64 65 78 20 70 65 6E 61 re is not a one-clock index pena 000028A0 6C 74 79 20 61 73 20 77 69 74 68 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 69 70 65 6C 69 6E lty as with the Intel486 pipelin 000028C0 65 2E 0D 0A 0D 0A 32 2E 33 2E 32 2E 20 43 61 63 68 65 73 0D 0A 0D 0A 54 68 65 20 6F 6E 2D 63 68 e.♪◙♪◙2.3.2. Caches♪◙♪◙The on-ch 000028E0 69 70 20 63 61 63 68 65 20 73 75 62 73 79 73 74 65 6D 20 63 6F 6E 73 69 73 74 73 20 6F 66 20 74 ip cache subsystem consists of t 00002900 77 6F 20 28 69 6E 73 74 72 75 63 74 69 6F 6E 20 61 6E 64 20 64 61 74 61 29 20 38 2D 4B 62 79 74 wo (instruction and data) 8-Kbyt 00002920 65 2C 20 74 77 6F 2D 77 61 79 20 73 65 74 20 61 73 73 6F 63 69 61 74 69 76 65 20 63 61 63 68 65 e, two-way set associative cache 00002940 73 20 77 69 74 68 20 61 20 63 61 63 68 65 20 6C 69 6E 65 20 6C 65 6E 67 74 68 20 6F 66 20 33 32 s with a cache line length of 32 00002960 20 62 79 74 65 73 2E 20 54 68 65 72 65 20 69 73 20 61 20 36 34 2D 62 69 74 20 77 69 64 65 20 65 bytes. There is a 64-bit wide e 00002980 78 74 65 72 6E 61 6C 20 64 61 74 61 20 62 75 73 20 69 6E 74 65 72 66 61 63 65 2E 20 54 68 65 20 xternal data bus interface. The 000029A0 63 61 63 68 65 73 20 65 6D 70 6C 6F 79 20 61 20 77 72 69 74 65 20 62 61 63 6B 20 6D 65 63 68 61 caches employ a write back mecha 000029C0 6E 69 73 6D 20 61 6E 64 20 61 6E 20 4C 52 55 20 72 65 70 6C 61 63 65 6D 65 6E 74 20 61 6C 67 6F nism and an LRU replacement algo 000029E0 72 69 74 68 6D 2E 20 54 68 65 20 64 61 74 61 20 63 61 63 68 65 20 63 6F 6E 73 69 73 74 73 20 6F rithm. The data cache consists o 00002A00 66 20 65 69 67 68 74 20 62 61 6E 6B 73 20 69 6E 74 65 72 6C 65 61 76 65 64 20 6F 6E 20 66 6F 75 f eight banks interleaved on fou 00002A20 72 2D 62 79 74 65 20 62 6F 75 6E 64 61 72 69 65 73 2E 20 20 54 68 65 20 64 61 74 61 20 63 61 63 r-byte boundaries. The data cac 00002A40 68 65 20 63 61 6E 20 62 65 20 61 63 63 65 73 73 65 64 20 73 69 6D 75 6C 74 61 6E 65 6F 75 73 6C he can be accessed simultaneousl 00002A60 79 20 66 72 6F 6D 20 62 6F 74 68 20 70 69 70 65 73 2C 20 61 73 20 6C 6F 6E 67 20 61 73 20 74 68 y from both pipes, as long as th 00002A80 65 20 72 65 66 65 72 65 6E 63 65 73 20 61 72 65 20 74 6F 20 64 69 66 66 65 72 65 6E 74 20 62 61 e references are to different ba 00002AA0 6E 6B 73 2E 20 54 68 65 20 6D 69 6E 69 6D 75 6D 20 64 65 6C 61 79 20 66 6F 72 20 61 20 63 61 63 nks. The minimum delay for a cac 00002AC0 68 65 20 6D 69 73 73 20 69 73 20 33 20 63 6C 6F 63 6B 73 2E 0D 0A 0D 0A 32 2E 33 2E 33 2E 20 20 he miss is 3 clocks.♪◙♪◙2.3.3. 00002AE0 49 6E 73 74 72 75 63 74 69 6F 6E 20 50 72 65 66 65 74 63 68 65 72 0D 0A 0D 0A 54 68 65 20 69 6E Instruction Prefetcher♪◙♪◙The in 00002B00 73 74 72 75 63 74 69 6F 6E 20 70 72 65 66 65 74 63 68 65 72 20 68 61 73 20 66 6F 75 72 20 62 75 struction prefetcher has four bu 00002B20 66 66 65 72 73 2C 20 65 61 63 68 20 6F 66 20 77 68 69 63 68 20 69 73 20 33 32 20 62 79 74 65 73 ffers, each of which is 32 bytes 00002B40 20 6C 6F 6E 67 2E 20 49 74 20 63 61 6E 20 66 65 74 63 68 20 61 6E 20 69 6E 73 74 72 75 63 74 69 long. It can fetch an instructi 00002B60 6F 6E 20 77 68 69 63 68 20 69 73 20 73 70 6C 69 74 20 61 6D 6F 6E 67 20 74 77 6F 20 63 61 63 68 on which is split among two cach 00002B80 65 20 6C 69 6E 65 73 20 77 69 74 68 20 6E 6F 20 70 65 6E 61 6C 74 79 2E 20 42 65 63 61 75 73 65 e lines with no penalty. Because 00002BA0 20 74 68 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 61 6E 64 20 64 61 74 61 20 63 61 63 68 65 73 the instruction and data caches 00002BC0 20 61 72 65 20 73 65 70 61 72 61 74 65 2C 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 70 72 65 66 65 are separate, instruction prefe 00002BE0 74 63 68 65 73 20 6E 6F 20 6C 6F 6E 67 65 72 20 63 6F 6E 66 6C 69 63 74 20 77 69 74 68 20 64 61 tches no longer conflict with da 00002C00 74 61 20 72 65 66 65 72 65 6E 63 65 73 20 66 6F 72 20 61 63 63 65 73 73 20 74 6F 20 74 68 65 20 ta references for access to the 00002C20 63 61 63 68 65 20 28 61 73 20 69 6E 20 74 68 65 20 63 61 73 65 20 6F 66 20 49 6E 74 65 6C 34 38 cache (as in the case of Intel48 00002C40 36 20 70 72 6F 63 65 73 73 6F 72 29 2E 0D 0A 0D 0A 32 2E 33 2E 34 2E 20 20 42 72 61 6E 63 68 20 6 processor).♪◙♪◙2.3.4. Branch 00002C60 54 61 72 67 65 74 20 42 75 66 66 65 72 0D 0A 0D 0A 54 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F Target Buffer♪◙♪◙The Pentium pro 00002C80 63 65 73 73 6F 72 20 65 6D 70 6C 6F 79 73 20 61 20 64 79 6E 61 6D 69 63 20 62 72 61 6E 63 68 20 cessor employs a dynamic branch 00002CA0 70 72 65 64 69 63 74 69 6F 6E 20 73 63 68 65 6D 65 20 77 69 74 68 20 61 20 32 35 36 2D 65 6E 74 prediction scheme with a 256-ent 00002CC0 72 79 20 42 72 61 6E 63 68 20 54 61 72 67 65 74 20 42 75 66 66 65 72 20 28 42 54 42 29 2E 20 20 ry Branch Target Buffer (BTB). 00002CE0 49 66 20 74 68 65 20 70 72 65 64 69 63 74 69 6F 6E 20 69 73 20 63 6F 72 72 65 63 74 2C 20 74 68 If the prediction is correct, th 00002D00 65 72 65 20 69 73 20 6E 6F 20 70 65 6E 61 6C 74 79 20 77 68 65 6E 20 65 78 65 63 75 74 69 6E 67 ere is no penalty when executing 00002D20 20 61 20 62 72 61 6E 63 68 20 69 6E 73 74 72 75 63 74 69 6F 6E 2E 20 20 54 68 65 72 65 20 69 73 a branch instruction. There is 00002D40 20 61 20 33 2D 63 79 63 6C 65 20 70 65 6E 61 6C 74 79 20 69 66 20 74 68 65 20 63 6F 6E 64 69 74 a 3-cycle penalty if the condit 00002D60 69 6F 6E 61 6C 20 62 72 61 6E 63 68 20 77 61 73 20 65 78 65 63 75 74 65 64 20 69 6E 20 74 68 65 ional branch was executed in the 00002D80 20 55 20 70 69 70 65 20 6F 72 20 61 20 34 2D 63 79 63 6C 65 20 70 65 6E 61 6C 74 79 20 69 66 20 U pipe or a 4-cycle penalty if 00002DA0 69 74 20 77 61 73 20 65 78 65 63 75 74 65 64 20 69 6E 20 74 68 65 20 56 20 20 70 69 70 65 2E 20 it was executed in the V pipe. 00002DC0 4D 69 73 70 72 65 64 69 63 74 65 64 20 63 61 6C 6C 73 20 61 6E 64 20 75 6E 63 6F 6E 64 69 74 69 Mispredicted calls and unconditi 00002DE0 6F 6E 61 6C 20 6A 75 6D 70 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 68 61 76 65 20 61 20 33 2D onal jump instructions have a 3- 00002E00 63 6C 6F 63 6B 20 70 65 6E 61 6C 74 79 20 69 6E 20 65 69 74 68 65 72 20 70 69 70 65 2E 20 4F 6E clock penalty in either pipe. On 00002E20 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 2C 20 74 61 6B 65 6E 20 62 the Intel486 processor, taken b 00002E40 72 61 6E 63 68 65 73 20 68 61 76 65 20 61 20 74 77 6F 2D 63 6C 6F 63 6B 20 70 65 6E 61 6C 74 79 ranches have a two-clock penalty 00002E60 2E 0D 0A 0D 0A 32 2E 33 2E 35 2E 20 50 69 70 65 6C 69 6E 65 64 20 46 6C 6F 61 74 69 6E 67 2D 50 .♪◙♪◙2.3.5. Pipelined Floating-P 00002E80 6F 69 6E 74 20 55 6E 69 74 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 oint Unit 00002EA0 20 20 20 20 20 20 0D 0A 0D 0A 54 68 65 20 6D 61 6A 6F 72 69 74 79 20 6F 66 20 74 68 65 20 66 72 ♪◙♪◙The majority of the fr 00002EC0 65 71 75 65 6E 74 6C 79 20 75 73 65 64 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 61 72 65 20 70 equently used instructions are p 00002EE0 69 70 65 6C 69 6E 65 64 20 73 6F 20 74 68 61 74 20 74 68 65 20 70 69 70 65 6C 69 6E 65 73 20 63 ipelined so that the pipelines c 00002F00 61 6E 20 61 63 63 65 70 74 20 61 20 6E 65 77 20 70 61 69 72 20 6F 66 20 6F 70 65 72 61 6E 64 73 an accept a new pair of operands 00002F20 20 65 76 65 72 79 20 63 79 63 6C 65 2E 20 54 68 65 72 65 66 6F 72 65 20 61 20 67 6F 6F 64 20 63 every cycle. Therefore a good c 00002F40 6F 64 65 20 67 65 6E 65 72 61 74 6F 72 20 63 61 6E 20 61 63 68 69 65 76 65 20 61 20 74 68 72 6F ode generator can achieve a thro 00002F60 75 67 68 70 75 74 20 6F 66 20 61 6C 6D 6F 73 74 20 31 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 70 ughput of almost 1 instruction p 00002F80 65 72 20 63 79 63 6C 65 20 28 6F 66 20 63 6F 75 72 73 65 20 74 68 69 73 20 61 73 73 75 6D 65 73 er cycle (of course this assumes 00002FA0 20 61 20 70 72 6F 67 72 61 6D 20 77 69 74 68 20 61 20 6D 6F 64 65 73 74 20 61 6D 6F 75 6E 74 20 a program with a modest amount 00002FC0 6F 66 20 6E 61 74 75 72 61 6C 20 70 61 72 61 6C 6C 65 6C 69 73 6D 21 29 2E 20 54 68 65 20 66 78 of natural parallelism!). The fx 00002FE0 63 68 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 63 61 6E 20 62 65 20 65 78 65 63 75 74 65 64 20 69 ch instruction can be executed i 00003000 6E 20 70 61 72 61 6C 6C 65 6C 20 77 69 74 68 20 74 68 65 20 63 6F 6D 6D 6F 6E 6C 79 20 75 73 65 n parallel with the commonly use 00003020 64 20 46 50 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 2C 20 77 68 69 63 68 20 6C 65 74 73 20 74 68 d FP instructions, which lets th 00003040 65 20 63 6F 64 65 20 67 65 6E 65 72 61 74 6F 72 20 6F 72 20 70 72 6F 67 72 61 6D 6D 65 72 20 74 e code generator or programmer t 00003060 72 65 61 74 20 74 68 65 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 73 74 61 63 6B 20 61 73 reat the floating-point stack as 00003080 20 61 20 72 65 67 75 6C 61 72 20 72 65 67 69 73 74 65 72 20 73 65 74 20 77 69 74 68 6F 75 74 20 a regular register set without 000030A0 61 6E 79 20 70 65 72 66 6F 72 6D 61 6E 63 65 20 64 65 67 72 61 64 61 74 69 6F 6E 2E 0D 0A 0D 0A any performance degradation.♪◙♪◙ 000030C0 57 69 74 68 20 74 68 65 20 73 75 70 65 72 73 63 61 6C 61 72 20 69 6D 70 6C 65 6D 65 6E 74 61 74 With the superscalar implementat 000030E0 69 6F 6E 2C 20 69 74 20 69 73 20 69 6D 70 6F 72 74 61 6E 74 20 74 6F 20 73 63 68 65 64 75 6C 65 ion, it is important to schedule 00003100 20 74 68 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 73 74 72 65 61 6D 20 74 6F 20 6D 61 78 69 6D the instruction stream to maxim 00003120 69 7A 65 20 74 68 65 20 75 73 61 67 65 20 6F 66 20 74 68 65 20 74 77 6F 20 69 6E 74 65 67 65 72 ize the usage of the two integer 00003140 20 70 69 70 65 6C 69 6E 65 73 2E 20 53 69 6E 63 65 20 65 61 63 68 20 6F 66 20 74 68 65 20 50 65 pipelines. Since each of the Pe 00003160 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 27 73 20 69 6E 74 65 67 65 72 20 70 69 70 65 6C 69 ntium processor's integer pipeli 00003180 6E 65 73 20 69 73 20 65 6E 68 61 6E 63 65 64 20 66 72 6F 6D 20 74 68 65 20 70 69 70 65 6C 69 6E nes is enhanced from the pipelin 000031A0 65 20 6F 66 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 2C 20 74 68 65 e of the Intel486 processor, the 000031C0 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 73 63 68 65 64 75 6C 69 6E 67 20 63 72 69 74 65 72 69 61 instruction scheduling criteria 000031E0 20 66 6F 72 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 20 69 73 20 61 20 for the Pentium processor is a 00003200 73 75 70 65 72 73 65 74 20 6F 66 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 superset of the Intel486 process 00003220 6F 72 20 72 65 71 75 69 72 65 6D 65 6E 74 73 2E 0D 0A 0D 0A 33 2E 20 49 6E 74 65 67 65 72 20 45 or requirements.♪◙♪◙3. Integer E 00003240 78 61 6D 70 6C 65 73 0D 0A 0D 0A 57 69 74 68 20 74 68 65 20 6F 76 65 72 76 69 65 77 20 6F 66 20 xamples♪◙♪◙With the overview of 00003260 74 68 65 20 49 6E 74 65 6C 33 38 36 2C 20 49 6E 74 65 6C 34 38 36 20 61 6E 64 20 50 65 6E 74 69 the Intel386, Intel486 and Penti 00003280 75 6D 20 70 72 6F 63 65 73 73 6F 72 73 20 69 6E 20 74 68 65 20 70 72 65 76 69 6F 75 73 20 73 65 um processors in the previous se 000032A0 63 74 69 6F 6E 2C 20 74 68 65 20 65 78 61 6D 70 6C 65 73 20 67 69 76 65 6E 20 69 6E 20 74 68 69 ction, the examples given in thi 000032C0 73 20 73 65 63 74 69 6F 6E 20 66 75 72 74 68 65 72 20 69 6C 6C 75 73 74 72 61 74 65 20 74 68 65 s section further illustrate the 000032E0 20 65 78 65 63 75 74 69 6F 6E 20 63 6C 6F 63 6B 20 63 79 63 6C 65 73 20 61 6D 6F 6E 67 20 76 61 execution clock cycles among va 00003300 72 69 6F 75 73 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 73 65 71 75 65 6E 63 65 73 2E 0D 0A 0D 0A rious instruction sequences.♪◙♪◙ 00003320 41 6C 6C 20 65 78 61 6D 70 6C 65 73 20 61 73 73 75 6D 65 20 61 20 31 30 30 25 20 63 61 63 68 65 All examples assume a 100% cache 00003340 20 68 69 74 20 72 61 74 65 20 61 6E 64 20 6E 6F 6E 2D 63 6F 6E 66 6C 69 63 74 69 6E 67 20 6D 65 hit rate and non-conflicting me 00003360 6D 6F 72 79 20 61 63 63 65 73 73 65 73 2E 20 41 20 33 32 2D 62 69 74 20 66 6C 61 74 20 61 64 64 mory accesses. A 32-bit flat add 00003380 72 65 73 73 20 6D 6F 64 65 6C 20 69 73 20 61 6C 73 6F 20 61 73 73 75 6D 65 64 2E 0D 0A 0D 0A 54 ress model is also assumed.♪◙♪◙T 000033A0 68 65 72 65 20 69 73 20 61 20 63 79 63 6C 65 20 63 6F 75 6E 74 20 6E 65 78 74 20 74 6F 20 65 61 here is a cycle count next to ea 000033C0 63 68 20 69 6E 73 74 72 75 63 74 69 6F 6E 2E 20 41 20 63 79 63 6C 65 20 63 6F 75 6E 74 20 61 70 ch instruction. A cycle count ap 000033E0 70 65 61 72 73 20 77 69 74 68 6F 75 74 20 61 6E 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 77 68 65 pears without an instruction whe 00003400 6E 20 74 68 65 72 65 20 69 73 20 61 20 70 69 70 65 20 73 74 61 6C 6C 2E 20 54 68 65 73 65 20 65 n there is a pipe stall. These e 00003420 78 61 6D 70 6C 65 73 20 61 6C 73 6F 20 61 73 73 75 6D 65 20 74 68 61 74 20 74 68 65 20 62 72 61 xamples also assume that the bra 00003440 6E 63 68 20 70 72 65 64 69 63 74 69 6F 6E 20 69 73 20 63 6F 72 72 65 63 74 2E 0D 0A 0D 0A 47 6F nch prediction is correct.♪◙♪◙Go 00003460 69 6E 67 20 74 68 72 6F 75 67 68 20 74 68 65 73 65 20 65 78 61 6D 70 6C 65 73 20 73 68 6F 75 6C ing through these examples shoul 00003480 64 20 67 69 76 65 20 79 6F 75 20 61 6E 20 69 6E 74 75 69 74 69 76 65 20 66 65 65 6C 20 66 6F 72 d give you an intuitive feel for 000034A0 20 68 6F 77 20 70 61 69 72 69 6E 67 20 77 6F 72 6B 73 20 6F 6E 20 74 68 65 20 50 65 6E 74 69 75 how pairing works on the Pentiu 000034C0 6D 20 70 72 6F 63 65 73 73 6F 72 20 61 6E 64 20 61 64 64 69 74 69 6F 6E 61 6C 20 69 6E 73 69 67 m processor and additional insig 000034E0 68 74 20 61 62 6F 75 74 20 73 6F 6D 65 20 6F 66 20 74 68 65 20 63 6F 6D 6D 6F 6E 20 64 65 6C 61 ht about some of the common dela 00003500 79 73 20 6F 6E 20 62 6F 74 68 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 61 6E 64 20 50 65 6E 74 ys on both the Intel486 and Pent 00003520 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 73 2E 0D 0A 0D 0A 43 20 73 6F 75 72 63 65 3A 0D 0A 0D 0A ium processors.♪◙♪◙C source:♪◙♪◙ 00003540 73 74 61 74 69 63 20 69 6E 74 20 61 5B 31 30 5D 2C 20 62 5B 31 30 5D 3B 0D 0A 69 6E 74 20 69 3B static int a[10], b[10];♪◙int i; 00003560 0D 0A 66 6F 72 20 28 69 3D 30 3B 20 69 3C 31 30 3B 20 69 2B 2B 29 20 7B 0D 0A 20 20 20 20 61 5B ♪◙for (i=0; i<10; i++) {♪◙ a[ 00003580 69 5D 20 3D 20 61 5B 69 5D 20 2B 20 31 3B 0D 0A 20 20 20 20 62 5B 69 5D 20 3D 20 62 5B 69 5D 20 i] = a[i] + 1;♪◙ b[i] = b[i] 000035A0 2B 20 31 3B 0D 0A 7D 0D 0A 0D 0A 54 68 65 72 65 20 61 72 65 20 76 61 72 69 6F 75 73 20 69 6E 73 + 1;♪◙}♪◙♪◙There are various ins 000035C0 74 72 75 63 74 69 6F 6E 20 73 65 71 75 65 6E 63 65 73 20 77 68 69 63 68 20 77 69 6C 6C 20 70 72 truction sequences which will pr 000035E0 6F 64 75 63 65 20 61 20 63 6F 72 72 65 63 74 20 70 72 6F 67 72 61 6D 2E 20 54 68 65 69 72 20 69 oduce a correct program. Their i 00003600 6E 64 69 76 69 64 75 61 6C 20 70 65 72 66 6F 72 6D 61 6E 63 65 2C 20 68 6F 77 65 76 65 72 2C 20 ndividual performance, however, 00003620 6D 61 79 20 76 61 72 79 20 63 6F 6E 73 69 64 65 72 61 62 6C 79 2E 0D 0A 0D 0A 48 65 72 65 20 61 may vary considerably.♪◙♪◙Here a 00003640 72 65 20 74 68 72 65 65 20 65 78 61 6D 70 6C 65 73 3A 0D 0A 0D 0A 53 65 71 75 65 6E 63 65 20 31 re three examples:♪◙♪◙Sequence 1 00003660 09 53 65 71 75 65 6E 63 65 20 32 09 53 65 71 75 65 6E 63 65 20 33 0D 0A 0D 0A 20 78 6F 72 20 65 ○Sequence 2○Sequence 3♪◙♪◙ xor e 00003680 61 78 2C 20 65 61 78 09 78 6F 72 20 65 61 78 2C 20 65 61 78 09 6D 6F 76 20 65 61 78 2C 20 2D 34 ax, eax○xor eax, eax○mov eax, -4 000036A0 30 0D 0A 0D 0A 54 6F 70 4F 66 4C 6F 6F 70 3A 20 09 54 6F 70 4F 66 4C 6F 6F 70 3A 09 54 6F 70 4F 0♪◙♪◙TopOfLoop: ○TopOfLoop:○TopO 000036C0 66 4C 6F 6F 70 3A 0D 0A 20 09 6D 6F 76 20 20 65 64 78 2C 20 65 61 78 09 09 69 6E 63 20 20 64 77 fLoop:♪◙ ○mov edx, eax○○inc dw 000036E0 6F 72 64 20 70 74 72 20 5B 65 61 78 2A 34 2B 61 5D 09 6D 6F 76 20 20 65 64 78 2C 20 5B 65 61 78 ord ptr [eax*4+a]○mov edx, [eax 00003700 2B 34 30 2B 61 5D 0D 0A 20 09 73 68 6C 20 20 65 64 78 2C 20 32 09 09 69 6E 63 20 20 64 77 6F 72 +40+a]♪◙ ○shl edx, 2○○inc dwor 00003720 64 20 70 74 72 20 5B 65 61 78 2A 34 2B 62 5D 09 6D 6F 76 20 20 65 63 78 2C 20 5B 65 61 78 2B 34 d ptr [eax*4+b]○mov ecx, [eax+4 00003740 30 2B 62 5D 0D 0A 20 09 69 6E 63 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 64 78 2B 61 5D 09 09 0+b]♪◙ ○inc dword ptr [edx+a]○○ 00003760 69 6E 63 20 20 65 61 78 09 09 69 6E 63 20 20 65 64 78 0D 0A 20 09 6D 6F 76 20 20 65 64 78 2C 20 inc eax○○inc edx♪◙ ○mov edx, 00003780 65 61 78 09 09 63 6D 70 20 20 65 61 78 2C 20 31 30 09 09 69 6E 63 20 20 65 63 78 0D 0A 20 09 73 eax○○cmp eax, 10○○inc ecx♪◙ ○s 000037A0 68 6C 20 20 65 64 78 2C 20 32 09 09 6A 6C 20 20 20 54 6F 70 4F 66 4C 6F 6F 70 09 09 6D 6F 76 20 hl edx, 2○○jl TopOfLoop○○mov 000037C0 20 5B 65 61 78 2B 34 30 2B 61 5D 2C 20 65 64 78 0D 0A 20 09 69 6E 63 20 20 64 77 6F 72 64 20 70 [eax+40+a], edx♪◙ ○inc dword p 000037E0 74 72 20 5B 65 64 78 2B 62 5D 09 09 6D 6F 76 20 20 5B 65 61 78 2B 34 30 2B 62 5D 2C 20 65 63 78 tr [edx+b]○○mov [eax+40+b], ecx 00003800 0D 0A 20 09 69 6E 63 20 20 65 61 78 20 09 09 61 64 64 20 20 65 61 78 2C 20 34 0D 0A 20 09 63 6D ♪◙ ○inc eax ○○add eax, 4♪◙ ○cm 00003820 70 20 20 65 61 78 2C 20 31 30 09 09 6A 6E 7A 20 20 54 6F 70 4F 66 4C 6F 6F 70 0D 0A 20 09 6A 31 p eax, 10○○jnz TopOfLoop♪◙ ○j1 00003840 20 20 20 54 6F 70 4F 66 4C 6F 6F 70 0D 0A 0D 0A 43 6F 64 65 20 53 65 71 75 65 6E 63 65 20 31 20 TopOfLoop♪◙♪◙Code Sequence 1 00003860 63 6F 75 6C 64 20 62 65 6E 65 66 69 74 20 66 72 6F 6D 20 63 6F 6D 6D 6F 6E 20 73 75 62 65 78 70 could benefit from common subexp 00003880 72 65 73 73 69 6F 6E 20 65 6C 69 6D 69 6E 61 74 69 6F 6E 2E 20 49 74 20 69 73 20 6E 6F 74 20 75 ression elimination. It is not u 000038A0 6E 6F 70 74 69 6D 69 7A 65 64 20 63 6F 64 65 2C 20 69 74 20 69 73 20 6A 75 73 74 20 6E 6F 74 20 noptimized code, it is just not 000038C0 74 68 6F 72 6F 75 67 68 6C 79 20 6F 70 74 69 6D 69 7A 65 64 2E 20 43 6F 64 65 20 74 68 61 74 20 thoroughly optimized. Code that 000038E0 69 73 20 75 6E 6F 70 74 69 6D 69 7A 65 64 20 77 6F 75 6C 64 20 6E 6F 74 20 6B 65 65 70 20 22 69 is unoptimized would not keep "i 00003900 22 20 69 6E 20 61 20 72 65 67 69 73 74 65 72 2E 0D 0A 0D 0A 43 6F 64 65 20 53 65 71 75 65 6E 63 " in a register.♪◙♪◙Code Sequenc 00003920 65 20 32 20 69 73 20 74 68 65 20 6D 6F 73 74 20 73 74 72 61 69 67 68 74 2D 66 6F 72 77 61 72 64 e 2 is the most straight-forward 00003940 20 73 74 79 6C 65 20 63 6F 64 65 2E 0D 0A 0D 0A 43 6F 64 65 20 53 65 71 75 65 6E 63 65 20 33 20 style code.♪◙♪◙Code Sequence 3 00003960 75 73 65 73 20 61 20 6C 6F 61 64 2F 73 74 6F 72 65 20 6D 6F 64 65 6C 2E 20 49 74 20 61 6C 73 6F uses a load/store model. It also 00003980 20 69 6E 63 6F 72 70 6F 72 61 74 65 73 20 73 6F 6D 65 20 69 6E 64 75 63 74 69 6F 6E 20 76 61 72 incorporates some induction var 000039A0 69 61 62 6C 65 20 65 6C 69 6D 69 6E 61 74 69 6F 6E 20 6F 70 74 69 6D 69 7A 61 74 69 6F 6E 73 20 iable elimination optimizations 000039C0 77 69 74 68 20 74 65 73 74 20 72 65 70 6C 61 63 65 6D 65 6E 74 2E 20 54 68 65 20 6C 6F 6F 70 20 with test replacement. The loop 000039E0 63 6F 75 6E 74 65 72 20 69 6E 20 65 61 78 20 63 6F 75 6E 74 73 20 75 70 20 74 6F 20 7A 65 72 6F counter in eax counts up to zero 00003A00 2E 20 20 57 68 65 6E 20 69 74 20 62 65 63 6F 6D 65 73 20 7A 65 72 6F 2C 20 74 68 65 20 6A 6E 7A . When it becomes zero, the jnz 00003A20 20 69 73 20 6E 6F 74 20 74 61 6B 65 6E 2E 20 54 68 69 73 20 63 6F 64 65 20 61 76 6F 69 64 73 20 is not taken. This code avoids 00003A40 74 68 65 20 63 6F 6D 70 61 72 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 2E 0D 0A 0D 0A 54 68 65 20 the compare instruction.♪◙♪◙The 00003A60 70 65 72 66 6F 72 6D 61 6E 63 65 20 6F 66 20 65 61 63 68 20 6F 66 20 74 68 65 73 65 20 63 6F 64 performance of each of these cod 00003A80 65 20 73 65 71 75 65 6E 63 65 73 20 69 73 20 65 78 61 6D 69 6E 65 64 20 6F 6E 20 62 6F 74 68 20 e sequences is examined on both 00003AA0 74 68 65 20 49 6E 74 65 6C 34 38 36 20 61 6E 64 20 50 65 6E 74 69 75 6D 20 0D 0A 70 72 6F 63 65 the Intel486 and Pentium ♪◙proce 00003AC0 73 73 6F 72 73 2E 0D 0A 0D 0A 33 2E 31 2E 20 20 43 6F 64 65 20 53 65 71 75 65 6E 63 65 20 31 2C ssors.♪◙♪◙3.1. Code Sequence 1, 00003AE0 20 49 6E 74 65 6C 34 38 36 20 50 72 6F 63 65 73 73 6F 72 0D 0A 0D 0A 54 68 65 20 73 68 6C 20 69 Intel486 Processor♪◙♪◙The shl i 00003B00 6E 73 74 72 75 63 74 69 6F 6E 20 74 61 6B 65 73 20 74 77 6F 20 63 79 63 6C 65 73 20 6F 6E 20 61 nstruction takes two cycles on a 00003B20 6E 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 2E 20 41 4C 55 20 6F 70 65 72 61 74 n Intel486 processor. ALU operat 00003B40 69 6F 6E 73 20 28 65 2E 67 2E 20 61 64 64 29 20 77 69 74 68 0D 0A 6D 65 6D 6F 72 79 20 72 65 73 ions (e.g. add) with♪◙memory res 00003B60 75 6C 74 73 20 74 61 6B 65 20 33 20 63 6C 6F 63 6B 73 3A 20 31 20 74 6F 20 6C 6F 61 64 2C 20 31 ults take 3 clocks: 1 to load, 1 00003B80 20 74 6F 20 61 64 64 2C 20 61 6E 64 20 31 20 74 6F 20 73 74 6F 72 65 2E 0D 0A 0D 0A 09 6D 6F 76 to add, and 1 to store.♪◙♪◙○mov 00003BA0 20 20 65 64 78 2C 20 65 61 78 20 09 3B 20 31 0D 0A 09 73 68 6C 20 20 65 64 78 2C 20 32 09 3B 20 edx, eax ○; 1♪◙○shl edx, 2○; 00003BC0 32 20 20 20 32 20 63 6C 6F 63 6B 20 69 6E 73 74 72 75 63 74 69 6F 6E 0D 0A 09 20 20 28 73 68 31 2 2 clock instruction♪◙○ (sh1 00003BE0 29 09 3B 20 33 0D 0A 09 69 6E 63 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 64 78 2B 61 5D 09 3B )○; 3♪◙○inc dword ptr [edx+a]○; 00003C00 20 34 20 20 20 33 20 63 6C 6F 63 6B 73 20 77 69 74 68 20 6D 65 6D 6F 72 79 20 6F 70 65 72 61 6E 4 3 clocks with memory operan 00003C20 64 0D 0A 09 20 20 28 69 6E 63 29 09 3B 20 35 20 20 20 20 20 70 6C 75 73 20 31 20 63 6C 6F 63 6B d♪◙○ (inc)○; 5 plus 1 clock 00003C40 20 66 6F 72 20 65 64 78 20 41 47 49 0D 0A 09 20 20 28 69 6E 63 29 09 3B 20 36 0D 0A 09 20 20 28 for edx AGI♪◙○ (inc)○; 6♪◙○ ( 00003C60 69 6E 63 29 09 3B 20 37 0D 0A 09 6D 6F 76 20 20 65 64 78 2C 20 65 61 78 09 3B 20 38 0D 0A 09 73 inc)○; 7♪◙○mov edx, eax○; 8♪◙○s 00003C80 68 6C 20 20 65 64 78 2C 20 32 09 3B 20 39 20 20 20 32 20 63 6C 6F 63 6B 20 69 6E 73 74 72 75 63 hl edx, 2○; 9 2 clock instruc 00003CA0 74 69 6F 6E 0D 0A 09 20 20 28 73 68 6C 29 09 3B 20 31 30 0D 0A 09 69 6E 63 20 20 64 77 6F 72 64 tion♪◙○ (shl)○; 10♪◙○inc dword 00003CC0 20 70 74 72 20 5B 65 64 78 2B 62 5D 09 3B 20 31 31 20 20 33 20 63 6C 6F 63 6B 73 20 77 69 74 68 ptr [edx+b]○; 11 3 clocks with 00003CE0 20 6D 65 6D 6F 72 79 20 6F 70 65 72 61 6E 64 0D 0A 09 20 20 28 69 6E 63 29 09 3B 20 31 32 20 20 memory operand♪◙○ (inc)○; 12 00003D00 20 20 70 6C 75 73 20 31 20 63 6C 6F 63 6B 20 66 6F 72 20 65 64 78 20 41 47 49 0D 0A 09 20 20 28 plus 1 clock for edx AGI♪◙○ ( 00003D20 69 6E 63 29 09 3B 20 31 33 0D 0A 09 20 20 28 69 6E 63 29 09 3B 20 31 34 0D 0A 09 69 6E 63 20 20 inc)○; 13♪◙○ (inc)○; 14♪◙○inc 00003D40 65 61 78 09 3B 20 31 35 0D 0A 09 63 6D 70 20 20 65 61 78 2C 20 31 30 09 3B 20 31 36 0D 0A 09 6A eax○; 15♪◙○cmp eax, 10○; 16♪◙○j 00003D60 6C 20 20 20 54 6F 70 4F 66 4C 6F 6F 70 20 09 3B 20 31 37 20 20 32 20 63 6C 6F 63 6B 73 20 62 65 l TopOfLoop ○; 17 2 clocks be 00003D80 63 61 75 73 65 20 6A 6C 20 69 73 20 70 72 65 66 69 78 65 64 0D 0A 09 09 3B 31 38 0D 0A 09 09 3B cause jl is prefixed♪◙○○;18♪◙○○; 00003DA0 20 31 39 20 20 62 72 61 6E 63 68 20 74 61 6B 65 6E 20 70 65 6E 61 6C 74 79 0D 0A 09 09 3B 20 32 19 branch taken penalty♪◙○○; 2 00003DC0 30 0D 0A 09 6D 6F 76 20 20 65 64 78 2C 20 65 61 78 09 3B 20 32 31 20 20 6E 65 78 74 20 69 74 65 0♪◙○mov edx, eax○; 21 next ite 00003DE0 72 61 74 69 6F 6E 0D 0A 0D 0A 54 6F 74 61 6C 3A 20 32 30 20 63 79 63 6C 65 73 0D 0A 0D 0A 43 79 ration♪◙♪◙Total: 20 cycles♪◙♪◙Cy 00003E00 63 6C 65 73 20 34 20 61 6E 64 20 31 31 20 68 61 64 20 61 6E 20 41 64 64 72 65 73 73 20 47 65 6E cles 4 and 11 had an Address Gen 00003E20 65 72 61 74 69 6F 6E 20 49 6E 74 65 72 6C 6F 63 6B 20 28 41 47 49 29 20 44 65 6C 61 79 2E 20 52 eration Interlock (AGI) Delay. R 00003E40 65 67 69 73 74 65 72 20 65 64 78 20 77 61 73 20 77 72 69 74 74 65 6E 20 69 6E 20 63 79 63 6C 65 egister edx was written in cycle 00003E60 20 33 20 61 6E 64 20 75 73 65 64 20 61 73 20 61 20 62 61 73 65 20 72 65 67 69 73 74 65 72 20 69 3 and used as a base register i 00003E80 6E 20 63 79 63 6C 65 20 35 2E 20 57 68 65 6E 20 61 20 72 65 67 69 73 74 65 72 20 69 73 20 75 73 n cycle 5. When a register is us 00003EA0 65 64 20 69 6E 20 61 6E 20 65 66 66 65 63 74 69 76 65 20 61 64 64 72 65 73 73 20 63 61 6C 63 75 ed in an effective address calcu 00003EC0 6C 61 74 69 6F 6E 20 69 6E 20 74 68 65 20 63 79 63 6C 65 20 61 66 74 65 72 20 74 68 65 20 72 65 lation in the cycle after the re 00003EE0 67 69 73 74 65 72 20 69 73 20 77 72 69 74 74 65 6E 2C 20 74 68 65 72 65 20 69 73 20 61 20 6F 6E gister is written, there is a on 00003F00 65 2D 63 6C 6F 63 6B 20 70 65 6E 61 6C 74 79 2E 20 54 68 69 73 20 68 61 70 70 65 6E 73 20 62 65 e-clock penalty. This happens be 00003F20 63 61 75 73 65 20 74 68 65 20 65 66 66 65 63 74 69 76 65 20 61 64 64 72 65 73 73 20 63 61 6C 63 cause the effective address calc 00003F40 75 6C 61 74 69 6F 6E 20 69 73 20 70 65 72 66 6F 72 6D 65 64 20 69 6E 20 74 68 65 20 44 32 20 73 ulation is performed in the D2 s 00003F60 74 61 67 65 20 6F 66 20 74 68 65 20 70 69 70 65 6C 69 6E 65 2E 0D 0A 0D 0A 57 69 74 68 20 74 68 tage of the pipeline.♪◙♪◙With th 00003F80 65 20 61 73 73 65 6D 62 6C 65 72 20 75 73 65 64 20 66 6F 72 20 74 68 69 73 20 63 6F 64 65 20 73 e assembler used for this code s 00003FA0 65 71 75 65 6E 63 65 2C 20 74 68 65 20 6A 6C 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 77 61 73 20 equence, the jl instruction was 00003FC0 61 20 22 6A 75 6D 70 20 6E 65 61 72 2C 22 20 6E 6F 74 20 61 20 22 6A 75 6D 70 20 73 68 6F 72 74 a "jump near," not a "jump short 00003FE0 2E 22 20 22 4A 75 6D 70 20 6E 65 61 72 22 20 69 73 20 61 20 30 66 20 70 72 65 66 69 78 65 64 20 ." "Jump near" is a 0f prefixed 00004000 69 6E 73 74 72 75 63 74 69 6F 6E 2E 20 50 72 65 66 69 78 65 64 20 69 6E 73 74 72 75 63 74 69 6F instruction. Prefixed instructio 00004020 6E 73 20 74 61 6B 65 20 61 6E 20 65 78 74 72 61 20 63 79 63 6C 65 20 6F 6E 20 74 68 65 20 49 6E ns take an extra cycle on the In 00004040 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 20 69 6E 20 74 68 65 20 44 31 20 73 74 61 67 65 tel486 processor in the D1 stage 00004060 2E 0D 0A 0D 0A 54 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 20 64 6F 65 73 .♪◙♪◙The Intel486 processor does 00004080 20 6E 6F 74 20 68 61 76 65 20 61 6E 79 20 62 72 61 6E 63 68 20 70 72 65 64 69 63 74 69 6F 6E 20 not have any branch prediction 000040A0 6D 65 63 68 61 6E 69 73 6D 2E 20 57 68 65 6E 65 76 65 72 20 6A 75 6D 70 73 20 61 72 65 20 74 61 mechanism. Whenever jumps are ta 000040C0 6B 65 6E 2C 0D 0A 74 68 65 72 65 20 69 73 20 61 20 32 2D 63 6C 6F 63 6B 20 70 65 6E 61 6C 74 79 ken,♪◙there is a 2-clock penalty 000040E0 20 28 43 79 63 6C 65 73 20 31 39 20 61 6E 64 20 32 30 29 2E 0D 0A 0D 0A 0C 33 2E 32 2E 20 20 43 (Cycles 19 and 20).♪◙♪◙♀3.2. C 00004100 6F 64 65 20 53 65 71 75 65 6E 63 65 20 31 2C 20 50 65 6E 74 69 75 6D 20 50 72 6F 63 65 73 73 6F ode Sequence 1, Pentium Processo 00004120 72 0D 0A 0D 0A 55 20 70 69 70 65 20 20 20 20 20 20 20 20 20 20 20 20 09 56 20 20 70 69 70 65 09 r♪◙♪◙U pipe ○V pipe○ 00004140 09 0D 0A 0D 0A 6D 6F 76 20 20 65 64 78 2C 20 65 61 78 09 09 3B 20 31 0D 0A 73 68 6C 20 20 65 64 ○♪◙♪◙mov edx, eax○○; 1♪◙shl ed 00004160 78 2C 20 32 20 09 09 3B 20 32 0D 0A 69 6E 63 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 64 78 2B x, 2 ○○; 2♪◙inc dword ptr [edx+ 00004180 61 5D 09 09 3B 20 33 20 20 20 33 20 63 6C 6F 63 6B 73 20 77 69 74 68 20 6D 65 6D 2E 20 6F 70 0D a]○○; 3 3 clocks with mem. op♪ 000041A0 0A 20 20 28 69 6E 63 29 09 09 3B 20 34 20 20 20 20 20 70 6C 75 73 20 31 20 66 6F 72 20 65 64 78 ◙ (inc)○○; 4 plus 1 for edx 000041C0 20 41 47 49 0D 0A 20 20 28 69 6E 63 29 09 09 3B 20 35 0D 0A 20 20 28 69 6E 63 29 09 6D 6F 76 20 AGI♪◙ (inc)○○; 5♪◙ (inc)○mov 000041E0 20 65 64 78 2C 20 65 61 78 09 3B 20 36 20 20 20 50 61 69 72 73 20 77 69 74 68 20 6C 61 73 74 20 edx, eax○; 6 Pairs with last 00004200 55 20 63 79 63 6C 65 0D 0A 73 68 6C 20 20 65 64 78 2C 20 32 09 09 3B 20 37 0D 0A 69 6E 63 20 20 U cycle♪◙shl edx, 2○○; 7♪◙inc 00004220 64 77 6F 72 64 20 70 74 72 20 5B 65 64 78 2B 62 5D 09 09 3B 20 38 20 20 20 33 20 63 6C 6F 63 6B dword ptr [edx+b]○○; 8 3 clock 00004240 73 20 77 69 74 68 20 6D 65 6D 2E 20 6F 70 0D 0A 20 20 28 69 6E 63 29 09 09 3B 20 39 20 20 20 20 s with mem. op♪◙ (inc)○○; 9 00004260 20 70 6C 75 73 20 6C 20 66 6F 72 20 65 64 78 20 41 47 49 0D 0A 20 20 28 69 6E 63 29 09 09 3B 20 plus l for edx AGI♪◙ (inc)○○; 00004280 31 30 0D 0A 20 20 28 69 6E 63 29 09 69 6E 63 20 20 65 61 78 09 3B 20 31 31 20 20 50 61 69 72 73 10♪◙ (inc)○inc eax○; 11 Pairs 000042A0 20 77 69 74 68 20 6C 61 73 74 20 55 20 63 79 63 6C 65 0D 0A 63 6D 70 20 20 65 61 78 2C 20 31 30 with last U cycle♪◙cmp eax, 10 000042C0 09 6A 6C 20 20 20 54 6F 70 4F 66 4C 6F 6F 70 09 3B 20 31 32 0D 0A 6D 6F 76 20 20 65 64 78 2C 20 ○jl TopOfLoop○; 12♪◙mov edx, 000042E0 65 61 78 09 09 3B 20 31 33 20 20 4E 65 78 74 20 69 74 65 72 61 74 69 6F 6E 0D 0A 0D 0A 54 6F 74 eax○○; 13 Next iteration♪◙♪◙Tot 00004300 61 6C 20 3A 31 32 20 63 79 63 6C 65 73 0D 0A 0D 0A 4E 6F 74 65 20 74 68 61 74 20 74 68 65 20 22 al :12 cycles♪◙♪◙Note that the " 00004320 73 68 69 66 74 22 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 74 61 6B 65 73 20 74 77 6F 20 63 6C 6F shift" instruction takes two clo 00004340 63 6B 73 20 6F 6E 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 20 61 6E cks on the Intel486 processor an 00004360 64 20 6F 6E 6C 79 20 6F 6E 65 20 6F 6E 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 d only one on the Pentium proces 00004380 73 6F 72 2E 20 54 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 20 68 61 73 20 73 sor. The Pentium processor has s 000043A0 70 65 63 69 61 6C 20 68 61 72 64 77 61 72 65 20 74 6F 20 61 76 6F 69 64 20 74 68 65 20 30 66 20 pecial hardware to avoid the 0f 000043C0 70 72 65 66 69 78 20 64 65 6C 61 79 20 6F 6E 20 6A 63 63 20 22 6E 65 61 72 22 20 69 6E 73 74 72 prefix delay on jcc "near" instr 000043E0 75 63 74 69 6F 6E 73 2E 20 49 74 20 61 6C 73 6F 20 63 61 6E 20 70 61 69 72 20 74 68 65 20 63 6F uctions. It also can pair the co 00004400 6D 70 61 72 65 20 61 6E 64 20 6A 75 6D 70 2C 20 65 76 65 6E 20 74 68 6F 75 67 68 20 63 6D 70 20 mpare and jump, even though cmp 00004420 77 72 69 74 65 73 20 61 20 63 6F 6E 64 69 74 69 6F 6E 20 66 6C 61 67 20 61 6E 64 20 6A 6C 20 72 writes a condition flag and jl r 00004440 65 61 64 73 20 69 74 2E 20 54 68 65 20 62 72 61 6E 63 68 20 70 72 65 64 69 63 74 69 6F 6E 20 68 eads it. The branch prediction h 00004460 61 72 64 77 61 72 65 2C 20 77 68 65 6E 20 69 74 20 70 72 65 64 69 63 74 73 20 74 68 65 20 62 72 ardware, when it predicts the br 00004480 61 6E 63 68 20 74 6F 20 62 65 20 74 61 6B 65 6E 2C 20 63 61 6E 20 65 78 65 63 75 74 65 20 74 68 anch to be taken, can execute th 000044A0 65 20 74 61 72 67 65 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 69 6E 20 74 68 65 20 63 79 63 6C e target instruction in the cycl 000044C0 65 20 66 6F 6C 6C 6F 77 69 6E 67 20 74 68 65 20 6A 75 6D 70 2E 20 57 68 65 6E 20 61 20 6D 75 6C e following the jump. When a mul 000044E0 74 69 70 6C 65 20 63 79 63 6C 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 69 6E 20 74 68 65 20 55 tiple cycle instruction in the U 00004500 20 70 69 70 65 20 70 61 69 72 73 20 77 69 74 68 20 61 6E 6F 74 68 65 72 20 69 6E 73 74 72 75 63 pipe pairs with another instruc 00004520 74 69 6F 6E 2C 20 74 68 65 20 6C 61 73 74 20 6D 65 6D 6F 72 79 20 6F 70 65 72 61 74 69 6F 6E 20 tion, the last memory operation 00004540 6F 66 20 74 68 65 20 55 20 70 69 70 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 70 61 69 72 73 20 of the U pipe instruction pairs 00004560 77 69 74 68 20 74 68 65 20 66 69 72 73 74 20 6F 70 65 72 61 74 69 6F 6E 20 6F 66 20 74 68 65 20 with the first operation of the 00004580 56 20 20 70 69 70 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 28 63 79 63 6C 65 73 20 36 20 61 6E V pipe instruction (cycles 6 an 000045A0 64 20 31 31 29 2E 0D 0A 0D 0A 33 2E 33 2E 20 20 43 6F 64 65 20 53 65 71 75 65 6E 63 65 20 32 2C d 11).♪◙♪◙3.3. Code Sequence 2, 000045C0 20 49 6E 74 65 6C 34 38 36 20 50 72 6F 63 65 73 73 6F 72 0D 0A 0D 0A 69 6E 63 20 20 64 77 6F 72 Intel486 Processor♪◙♪◙inc dwor 000045E0 64 20 70 74 72 20 5B 65 61 78 2A 34 2B 61 5D 20 09 3B 20 31 20 20 20 33 20 63 6C 6F 63 6B 73 20 d ptr [eax*4+a] ○; 1 3 clocks 00004600 77 69 74 68 20 6D 65 6D 6F 72 79 20 6F 70 65 72 61 6E 64 0D 0A 20 20 28 69 6E 63 29 09 3B 20 32 with memory operand♪◙ (inc)○; 2 00004620 20 20 20 20 20 70 6C 75 73 20 31 20 66 6F 72 20 69 6E 64 65 78 69 6E 67 0D 0A 20 20 28 69 6E 63 plus 1 for indexing♪◙ (inc 00004640 29 09 3B 20 33 0D 0A 20 20 28 69 6E 63 29 09 3B 20 34 0D 0A 69 6E 63 20 20 64 77 6F 72 64 20 70 )○; 3♪◙ (inc)○; 4♪◙inc dword p 00004660 74 72 20 5B 65 61 78 2A 34 2B 62 5D 09 3B 20 35 20 20 20 33 20 63 6C 6F 63 6B 73 20 77 69 74 68 tr [eax*4+b]○; 5 3 clocks with 00004680 20 6D 65 6D 6F 72 79 20 6F 70 65 72 61 6E 64 0D 0A 20 20 28 69 6E 63 29 09 3B 20 36 20 20 20 20 memory operand♪◙ (inc)○; 6 000046A0 20 70 6C 75 73 20 31 20 66 6F 72 20 69 6E 64 65 78 69 6E 67 0D 0A 20 20 28 69 6E 63 29 09 3B 20 plus 1 for indexing♪◙ (inc)○; 000046C0 37 0D 0A 20 20 28 69 6E 63 29 09 3B 20 38 0D 0A 69 6E 63 20 20 65 61 78 09 3B 20 39 0D 0A 63 6D 7♪◙ (inc)○; 8♪◙inc eax○; 9♪◙cm 000046E0 70 20 20 65 61 78 2C 20 31 30 09 3B 20 31 30 0D 0A 6A 6C 20 20 20 54 6F 70 4F 66 4C 6F 6F 70 09 p eax, 10○; 10♪◙jl TopOfLoop○ 00004700 3B 20 31 31 20 20 32 20 63 6C 6F 63 6B 73 20 62 65 63 61 75 73 65 20 6A 6C 20 69 73 20 70 72 65 ; 11 2 clocks because jl is pre 00004720 66 69 78 65 64 0D 0A 09 3B 20 31 32 0D 0A 09 3B 20 31 33 20 20 42 72 61 6E 63 68 20 74 61 6B 65 fixed♪◙○; 12♪◙○; 13 Branch take 00004740 6E 20 70 65 6E 61 6C 74 79 0D 0A 09 3B 20 31 34 0D 0A 69 6E 63 20 20 64 77 6F 72 64 20 70 74 72 n penalty♪◙○; 14♪◙inc dword ptr 00004760 20 5B 65 61 78 2A 34 2B 61 5D 09 3B 20 31 35 20 20 4E 65 78 74 20 69 74 65 72 61 74 69 6F 6E 0D [eax*4+a]○; 15 Next iteration♪ 00004780 0A 0D 0A 54 6F 74 61 6C 20 3A 31 34 20 63 79 63 6C 65 73 0D 0A 0D 0A 4F 6E 20 74 68 65 20 49 6E ◙♪◙Total :14 cycles♪◙♪◙On the In 000047A0 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 2C 20 77 68 65 6E 65 76 65 72 20 61 6E 20 69 6E tel486 processor, whenever an in 000047C0 64 65 78 20 72 65 67 69 73 74 65 72 20 69 73 20 75 73 65 64 20 69 6E 20 61 6E 20 65 66 66 65 63 dex register is used in an effec 000047E0 74 69 76 65 20 61 64 64 72 65 73 73 20 63 61 6C 63 75 6C 61 74 69 6F 6E 2C 0D 0A 74 68 65 72 65 tive address calculation,♪◙there 00004800 20 69 73 20 61 20 6F 6E 65 2D 63 6C 6F 63 6B 20 70 65 6E 61 6C 74 79 20 69 6E 20 74 68 65 20 44 is a one-clock penalty in the D 00004820 32 20 73 74 61 67 65 20 28 43 79 63 6C 65 73 20 31 20 61 6E 64 20 35 29 2E 20 54 68 69 73 20 64 2 stage (Cycles 1 and 5). This d 00004840 6F 65 73 20 6E 6F 74 20 61 70 70 6C 79 20 74 6F 20 62 61 73 65 0D 0A 72 65 67 69 73 74 65 72 73 oes not apply to base♪◙registers 00004860 2E 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 33 2E 34 2E 20 20 43 6F 64 65 20 73 65 71 75 .♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙3.4. Code sequ 00004880 65 6E 63 65 20 32 2C 20 50 65 6E 74 69 75 6D 20 50 72 6F 63 65 73 73 6F 72 0D 0A 0D 0A 55 20 70 ence 2, Pentium Processor♪◙♪◙U p 000048A0 69 70 65 20 20 20 20 20 20 20 20 20 20 20 20 20 09 20 56 20 20 70 69 70 65 20 0D 0A 0D 0A 69 6E ipe ○ V pipe ♪◙♪◙in 000048C0 63 20 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 61 78 2A 34 2B 61 5D 20 09 3B 20 31 20 33 20 63 c dword ptr [eax*4+a] ○; 1 3 c 000048E0 6C 6F 63 6B 73 20 77 69 74 68 20 6D 65 6D 2E 20 6F 70 2E 0D 0A 20 20 28 69 6E 63 29 09 09 3B 20 locks with mem. op.♪◙ (inc)○○; 00004900 32 0D 0A 20 20 28 69 6E 63 29 09 69 6E 63 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 61 78 2A 34 2♪◙ (inc)○inc dword ptr [eax*4 00004920 2B 62 5D 09 3B 20 33 20 31 73 74 20 56 20 70 61 69 72 73 20 77 69 74 68 20 6C 61 73 74 20 55 0D +b]○; 3 1st V pairs with last U♪ 00004940 0A 20 09 20 20 28 69 6E 63 29 09 3B 20 34 0D 0A 09 20 20 28 69 6E 63 29 09 3B 20 35 0D 0A 69 6E ◙ ○ (inc)○; 4♪◙○ (inc)○; 5♪◙in 00004960 63 20 20 20 20 65 61 78 09 09 3B 20 36 0D 0A 63 6D 70 20 20 20 20 65 61 78 2C 20 31 30 09 6A 6C c eax○○; 6♪◙cmp eax, 10○jl 00004980 20 20 54 6F 70 4F 66 4C 6F 6F 70 09 3B 20 37 0D 0A 69 6E 63 20 20 20 20 64 77 6F 72 64 20 70 74 TopOfLoop○; 7♪◙inc dword pt 000049A0 72 20 5B 65 61 78 2A 34 2B 61 5D 09 3B 20 38 20 4E 65 78 74 20 69 74 65 72 61 74 69 6F 6E 0D 0A r [eax*4+a]○; 8 Next iteration♪◙ 000049C0 0D 0A 54 6F 74 61 6C 3A 20 37 20 63 79 63 6C 65 73 0D 0A 0D 0A 54 68 65 20 69 6E 63 20 65 61 78 ♪◙Total: 7 cycles♪◙♪◙The inc eax 000049E0 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 61 74 20 63 79 63 6C 65 20 36 20 64 69 64 20 6E 6F 74 20 instruction at cycle 6 did not 00004A00 70 61 69 72 20 77 69 74 68 20 74 68 65 20 63 6D 70 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 62 65 pair with the cmp instruction be 00004A20 63 61 75 73 65 20 6F 66 20 61 20 72 65 67 69 73 74 65 72 20 64 65 70 65 6E 64 65 6E 63 65 2E 20 cause of a register dependence. 00004A40 4F 74 68 65 72 20 74 68 61 6E 20 69 6E 20 61 20 66 65 77 20 73 70 65 63 69 61 6C 20 63 61 73 65 Other than in a few special case 00004A60 73 20 28 73 75 63 68 20 61 73 20 63 6D 70 2D 6A 6D 70 29 2C 20 61 20 72 65 67 69 73 74 65 72 20 s (such as cmp-jmp), a register 00004A80 63 61 6E 6E 6F 74 20 62 65 20 61 63 63 65 73 73 65 64 20 75 6E 74 69 6C 20 74 68 65 20 63 79 63 cannot be accessed until the cyc 00004AA0 6C 65 20 61 66 74 65 72 20 69 74 20 69 73 20 77 72 69 74 74 65 6E 2E 0D 0A 0D 0A 33 2E 35 2E 20 le after it is written.♪◙♪◙3.5. 00004AC0 20 43 6F 64 65 20 53 65 71 75 65 6E 63 65 20 33 2C 20 49 6E 74 65 6C 34 38 36 20 50 72 6F 63 65 Code Sequence 3, Intel486 Proce 00004AE0 73 73 6F 72 0D 0A 0D 0A 09 6D 6F 76 20 20 65 64 78 2C 20 5B 65 61 78 2B 34 30 2B 61 5D 09 3B 20 ssor♪◙♪◙○mov edx, [eax+40+a]○; 00004B00 31 0D 0A 09 09 3B 20 32 20 20 20 46 69 6C 6C 20 70 72 65 66 65 74 63 68 20 62 75 66 66 65 72 0D 1♪◙○○; 2 Fill prefetch buffer♪ 00004B20 0A 09 6D 6F 76 20 20 65 63 78 2C 20 5B 65 61 78 2B 34 30 2B 62 5D 09 3B 20 33 0D 0A 09 69 6E 63 ◙○mov ecx, [eax+40+b]○; 3♪◙○inc 00004B40 20 20 65 64 78 09 3B 20 34 0D 0A 09 69 6E 63 20 20 65 63 78 09 3B 20 35 0D 0A 09 6D 6F 76 20 20 edx○; 4♪◙○inc ecx○; 5♪◙○mov 00004B60 5B 65 61 78 2B 34 30 2B 61 5D 2C 20 65 64 78 09 3B 20 36 0D 0A 09 6D 6F 76 20 20 5B 65 61 78 2B [eax+40+a], edx○; 6♪◙○mov [eax+ 00004B80 34 30 2B 62 5D 2C 20 65 63 78 20 09 3B 20 37 0D 0A 09 61 64 64 20 20 65 61 78 2C 20 34 09 3B 20 40+b], ecx ○; 7♪◙○add eax, 4○; 00004BA0 38 0D 0A 09 6A 6E 7A 20 20 54 6F 70 4F 66 4C 6F 6F 70 09 3B 20 39 20 20 20 50 72 65 66 69 78 20 8♪◙○jnz TopOfLoop○; 9 Prefix 00004BC0 6F 6E 20 6A 6E 7A 0D 0A 09 09 3B 20 31 30 0D 0A 09 09 3B 20 31 31 20 20 42 72 61 6E 63 68 20 70 on jnz♪◙○○; 10♪◙○○; 11 Branch p 00004BE0 65 6E 61 6C 74 79 0D 0A 20 20 20 20 09 09 3B 20 31 32 0D 0A 09 6D 6F 76 20 20 65 64 78 2C 20 5B enalty♪◙ ○○; 12♪◙○mov edx, [ 00004C00 65 61 78 2B 34 30 2B 61 5D 09 3B 20 31 33 20 20 4E 65 78 74 20 69 74 65 72 61 74 69 6F 6E 0D 0A eax+40+a]○; 13 Next iteration♪◙ 00004C20 0D 0A 54 6F 74 61 6C 20 3A 20 31 32 20 63 79 63 6C 65 73 0D 0A 0D 0A 54 68 65 20 64 65 6C 61 79 ♪◙Total : 12 cycles♪◙♪◙The delay 00004C40 20 61 74 20 63 6C 6F 63 6B 20 32 20 69 73 20 63 61 75 73 65 64 20 62 79 20 61 20 6D 69 73 73 20 at clock 2 is caused by a miss 00004C60 69 6E 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 27 73 20 70 72 65 66 in the Intel486 processor's pref 00004C80 65 74 63 68 20 62 75 66 66 65 72 2E 20 54 68 65 20 70 72 65 76 69 6F 75 73 20 74 77 6F 20 65 78 etch buffer. The previous two ex 00004CA0 61 6D 70 6C 65 73 20 68 61 64 20 61 20 73 69 6D 69 6C 61 72 20 70 65 6E 61 6C 74 79 2C 20 62 75 amples had a similar penalty, bu 00004CC0 74 20 69 74 20 77 61 73 20 68 69 64 64 65 6E 20 62 79 20 74 68 65 20 32 2D 63 6C 6F 63 6B 73 20 t it was hidden by the 2-clocks 00004CE0 75 73 65 64 20 66 6F 72 20 74 68 65 20 73 68 6C 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 69 6E 20 used for the shl instruction in 00004D00 63 6F 64 65 20 73 65 71 75 65 6E 63 65 20 31 2C 20 61 6E 64 20 62 79 20 74 68 65 20 69 6E 64 65 code sequence 1, and by the inde 00004D20 78 20 70 65 6E 61 6C 74 79 20 69 6E 20 63 6F 64 65 20 73 65 71 75 65 6E 63 65 20 32 2E 0D 0A 0D x penalty in code sequence 2.♪◙♪ 00004D40 0A 33 2E 36 2E 20 20 43 6F 64 65 20 53 65 71 75 65 6E 63 65 20 33 2C 20 50 65 6E 74 69 75 6D 20 ◙3.6. Code Sequence 3, Pentium 00004D60 50 72 6F 63 65 73 73 6F 72 0D 0A 0D 0A 55 20 70 69 70 65 20 09 20 20 56 20 20 70 69 70 65 0D 0A Processor♪◙♪◙U pipe ○ V pipe♪◙ 00004D80 0D 0A 6D 6F 76 20 20 65 64 78 2C 20 5B 65 61 78 2B 34 30 2B 61 5D 09 6D 6F 76 20 20 65 63 78 2C ♪◙mov edx, [eax+40+a]○mov ecx, 00004DA0 20 5B 65 61 78 2B 34 30 2B 62 5D 09 3B 20 31 0D 0A 69 6E 63 20 20 65 64 78 09 69 6E 63 20 20 65 [eax+40+b]○; 1♪◙inc edx○inc e 00004DC0 63 78 09 3B 20 32 0D 0A 6D 6F 76 20 20 5B 65 61 78 2B 34 30 2B 61 5D 2C 20 65 64 78 09 6D 6F 76 cx○; 2♪◙mov [eax+40+a], edx○mov 00004DE0 20 20 5B 65 61 78 2B 34 30 2B 62 5D 2C 20 65 63 78 09 3B 20 33 0D 0A 61 64 64 20 20 65 61 78 2C [eax+40+b], ecx○; 3♪◙add eax, 00004E00 20 34 09 6A 6E 7A 20 20 54 6F 70 4F 66 4C 6F 6F 70 09 3B 20 34 0D 0A 6D 6F 76 20 20 65 64 78 2C 4○jnz TopOfLoop○; 4♪◙mov edx, 00004E20 20 5B 65 61 78 2B 34 30 2B 61 5D 09 6D 6F 76 20 20 65 63 78 2C 20 5B 65 61 78 2B 34 30 2B 62 5D [eax+40+a]○mov ecx, [eax+40+b] 00004E40 09 3B 20 35 20 41 47 49 20 6F 6E 20 65 61 78 20 77 69 74 68 0D 0A 20 20 28 6D 6F 76 29 20 20 20 ○; 5 AGI on eax with♪◙ (mov) 00004E60 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 09 20 20 28 6D 6F 76 29 09 3B 20 36 20 6E ○ (mov)○; 6 n 00004E80 65 78 74 20 69 74 65 72 61 74 69 6F 6E 0D 0A 0D 0A 54 6F 74 61 6C 3A 20 35 20 63 79 63 6C 65 73 ext iteration♪◙♪◙Total: 5 cycles 00004EA0 0D 0A 0D 0A 54 68 65 20 70 72 65 66 65 74 63 68 20 62 75 66 66 65 72 20 64 65 6C 61 79 20 6F 6E ♪◙♪◙The prefetch buffer delay on 00004EC0 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 20 69 73 20 6E 6F 20 6C 6F the Intel486 processor is no lo 00004EE0 6E 67 65 72 20 72 65 6C 65 76 61 6E 74 2E 20 54 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 nger relevant. The Pentium proce 00004F00 73 73 6F 72 20 68 61 73 20 6D 6F 72 65 20 70 72 65 66 65 74 63 68 20 62 75 66 66 65 72 73 20 61 ssor has more prefetch buffers a 00004F20 6E 64 20 64 69 66 66 65 72 65 6E 74 20 61 6C 69 67 6E 6D 65 6E 74 20 63 61 70 61 62 69 6C 69 74 nd different alignment capabilit 00004F40 69 65 73 2E 20 49 6E 20 74 68 65 20 65 78 61 6D 70 6C 65 20 61 62 6F 76 65 2C 20 74 68 65 20 6C ies. In the example above, the l 00004F60 6F 6F 70 20 63 6F 6E 74 72 6F 6C 20 69 73 20 64 65 74 65 72 6D 69 6E 65 64 20 62 79 20 74 68 65 oop control is determined by the 00004F80 20 61 64 64 20 65 61 78 2C 20 34 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 73 65 74 74 69 6E 67 20 add eax, 4 instruction setting 00004FA0 74 68 65 20 7A 65 72 6F 20 63 6F 6E 64 69 74 69 6F 6E 20 63 6F 64 65 20 61 73 20 69 74 20 63 6F the zero condition code as it co 00004FC0 75 6E 74 73 20 75 70 20 74 6F 20 7A 65 72 6F 2E 0D 0A 0D 0A 54 68 65 72 65 20 69 73 20 61 6E 20 unts up to zero.♪◙♪◙There is an 00004FE0 41 47 49 20 6F 6E 20 65 61 78 20 62 65 63 61 75 73 65 20 74 68 65 20 61 64 64 20 69 6E 20 63 79 AGI on eax because the add in cy 00005000 63 6C 65 20 34 20 77 72 69 74 65 73 20 74 6F 20 65 61 78 20 61 6E 64 20 62 6F 74 68 20 6D 6F 76 cle 4 writes to eax and both mov 00005020 27 20 73 20 69 6E 20 63 79 63 6C 65 20 35 20 72 65 66 65 72 65 6E 63 65 20 69 74 2C 20 65 76 65 ' s in cycle 5 reference it, eve 00005040 6E 20 74 68 6F 75 67 68 20 74 68 65 72 65 20 69 73 20 61 20 62 72 61 6E 63 68 20 69 6E 20 62 65 n though there is a branch in be 00005060 74 77 65 65 6E 2E 20 4F 6E 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 tween. On the Intel486 processor 00005080 2C 20 41 47 6C 27 73 20 6F 6E 6C 79 20 68 61 70 70 65 6E 20 62 65 74 77 65 65 6E 20 61 64 6A 61 , AGl's only happen between adja 000050A0 63 65 6E 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 2E 20 4F 6E 20 74 68 65 20 50 65 6E 74 69 75 cent instructions. On the Pentiu 000050C0 6D 20 70 72 6F 63 65 73 73 6F 72 2C 20 74 68 65 72 65 20 63 61 6E 20 62 65 20 74 77 6F 20 69 6E m processor, there can be two in 000050E0 73 74 72 75 63 74 69 6F 6E 73 20 69 6E 20 62 65 74 77 65 65 6E 20 61 6E 64 20 73 74 69 6C 6C 20 structions in between and still 00005100 62 65 20 61 6E 20 41 47 49 3B 20 66 6F 72 20 65 78 61 6D 70 6C 65 2C 20 62 65 74 77 65 65 6E 20 be an AGI; for example, between 00005120 61 20 55 20 70 69 70 65 20 61 64 64 20 69 6E 20 63 79 63 6C 65 20 6E 20 61 6E 64 20 61 20 56 20 a U pipe add in cycle n and a V 00005140 20 70 69 70 65 20 6D 6F 76 20 74 68 61 74 20 75 73 65 73 20 74 68 65 20 72 65 73 75 6C 74 20 6F pipe mov that uses the result o 00005160 66 20 74 68 65 20 61 64 64 20 61 73 20 61 20 62 61 73 65 20 69 6E 20 63 79 63 6C 65 20 6E 2B 31 f the add as a base in cycle n+1 00005180 2E 20 54 68 65 20 67 65 6E 65 72 61 6C 20 72 75 6C 65 20 69 73 20 74 68 61 6E 20 61 6E 20 41 47 . The general rule is than an AG 000051A0 49 20 77 69 6C 6C 20 6F 63 63 75 72 20 77 68 65 6E 20 61 6E 79 20 69 6E 73 74 72 75 63 74 69 6F I will occur when any instructio 000051C0 6E 20 69 6E 20 63 79 63 6C 65 20 6E 20 77 72 69 74 65 73 20 74 6F 20 61 20 72 65 67 69 73 74 65 n in cycle n writes to a registe 000051E0 72 20 74 68 61 74 20 69 73 20 75 73 65 64 20 69 6E 20 61 6E 20 65 66 66 65 63 74 69 76 65 20 61 r that is used in an effective a 00005200 64 64 72 65 73 73 20 63 61 6C 63 75 6C 61 74 69 6F 6E 20 69 6E 20 61 6E 79 20 69 6E 73 74 72 75 ddress calculation in any instru 00005220 63 74 69 6F 6E 20 69 6E 20 63 79 63 6C 65 20 6E 2B 31 2E 20 54 68 69 73 20 69 73 20 62 65 63 61 ction in cycle n+1. This is beca 00005240 75 73 65 20 74 68 65 20 65 66 66 65 63 74 69 76 65 20 61 64 64 72 65 73 73 20 63 61 6C 63 75 6C use the effective address calcul 00005260 61 74 69 6F 6E 20 69 73 20 70 65 72 66 6F 72 6D 65 64 20 69 6E 20 44 32 2E 0D 0A 0D 0A 49 6E 20 ation is performed in D2.♪◙♪◙In 00005280 61 20 63 6F 6D 70 69 6C 65 72 27 73 20 69 6E 74 65 72 6D 65 64 69 61 74 65 20 72 65 70 72 65 73 a compiler's intermediate repres 000052A0 65 6E 74 61 74 69 6F 6E 20 6F 66 20 74 68 65 20 70 72 6F 67 72 61 6D 20 62 65 66 6F 72 65 20 69 entation of the program before i 000052C0 6E 73 74 72 75 63 74 69 6F 6E 20 73 63 68 65 64 75 6C 69 6E 67 20 28 72 65 6F 72 64 65 72 69 6E nstruction scheduling (reorderin 000052E0 67 29 2C 20 6F 6E 65 20 6D 69 67 68 74 20 65 78 70 65 63 74 20 74 68 65 20 6F 72 64 65 72 20 66 g), one might expect the order f 00005300 6F 72 20 73 65 71 75 65 6E 63 65 20 33 20 74 6F 20 62 65 3A 0D 0A 0D 0A 6C 6F 61 64 20 5B 61 2B or sequence 3 to be:♪◙♪◙load [a+ 00005320 65 61 78 2B 34 30 5D 20 20 20 20 20 20 20 20 20 20 20 20 6C 6F 61 64 20 5B 62 2B 65 61 78 2B 34 eax+40] load [b+eax+4 00005340 30 5D 0D 0A 20 20 20 20 20 20 20 7C 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 0]♪◙ | 00005360 20 20 20 20 20 20 20 20 20 7C 0D 0A 20 20 20 20 20 20 20 7C 20 20 20 20 20 20 20 20 20 20 20 20 |♪◙ | 00005380 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 7C 0D 0A 20 20 20 20 20 20 20 61 64 64 20 31 |♪◙ add 1 000053A0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 61 64 64 20 31 0D 0A 20 20 20 add 1♪◙ 000053C0 20 20 20 20 20 7C 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 | 000053E0 20 20 20 7C 0D 0A 20 20 20 20 20 20 20 20 7C 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 |♪◙ | 00005400 20 20 20 20 20 20 20 20 20 20 20 20 7C 0D 0A 20 20 20 20 20 73 74 6F 72 65 20 5B 61 2B 65 61 78 |♪◙ store [a+eax 00005420 2B 34 30 5D 20 20 20 20 20 20 73 74 6F 72 65 20 5B 62 2B 65 61 78 2B 34 30 5D 0D 0A 20 20 20 20 +40] store [b+eax+40]♪◙ 00005440 20 20 20 20 20 20 20 20 20 20 20 20 7C 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 7C 20 | | 00005460 20 20 20 20 20 20 20 20 20 20 20 0D 0A 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 7C 20 20 ♪◙ | 00005480 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 7C 20 20 20 20 20 20 20 20 20 20 20 20 0D 0A 20 20 | ♪◙ 000054A0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 61 64 64 20 20 65 61 78 2C 20 31 0D 0A 20 20 add eax, 1♪◙ 000054C0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 7C 0D 0A 20 20 20 20 20 20 |♪◙ 000054E0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 7C 0D 0A 20 20 20 20 20 20 20 20 20 20 |♪◙ 00005500 20 20 20 20 20 20 20 20 20 20 20 63 6D 70 20 20 31 30 0D 0A 20 20 20 20 20 20 20 20 20 20 20 20 cmp 10♪◙ 00005520 20 20 20 20 20 20 20 20 20 20 20 20 20 7C 0D 0A 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 |♪◙ 00005540 20 20 20 20 20 20 20 20 20 7C 0D 0A 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 |♪◙ 00005560 20 20 20 6A 75 6D 70 0D 0A 0D 0A 52 65 6F 72 64 65 72 69 6E 67 20 74 68 69 73 20 69 6E 74 65 72 jump♪◙♪◙Reordering this inter 00005580 6D 65 64 69 61 74 65 20 63 6F 64 65 20 74 6F 20 6F 62 74 61 69 6E 20 74 68 65 20 61 73 73 65 6D mediate code to obtain the assem 000055A0 62 6C 79 20 63 6F 64 65 20 73 68 6F 77 6E 20 65 61 72 6C 69 65 72 20 69 6E 76 6F 6C 76 65 73 20 bly code shown earlier involves 000055C0 6D 6F 76 69 6E 67 20 74 68 65 20 6C 6F 61 64 20 66 72 6F 6D 20 22 62 22 20 69 6E 20 66 72 6F 6E moving the load from "b" in fron 000055E0 74 20 6F 66 20 74 68 65 20 73 74 6F 72 65 20 69 6E 74 6F 20 22 61 2E 22 20 49 6E 73 74 72 75 63 t of the store into "a." Instruc 00005600 74 69 6F 6E 20 72 65 6F 72 64 65 72 69 6E 67 20 72 65 71 75 69 72 65 73 20 6B 6E 6F 77 69 6E 67 tion reordering requires knowing 00005620 20 74 68 61 74 20 6D 65 6D 6F 72 79 20 6F 70 65 72 61 6E 64 73 20 61 72 65 20 69 6E 64 65 70 65 that memory operands are indepe 00005640 6E 64 65 6E 74 2E 20 49 6E 20 74 68 69 73 20 63 61 73 65 2C 20 69 74 20 63 61 6E 20 62 65 20 65 ndent. In this case, it can be e 00005660 61 73 69 6C 79 20 70 72 6F 76 65 6E 20 74 68 61 74 20 65 6C 65 6D 65 6E 74 73 20 6F 66 20 22 61 asily proven that elements of "a 00005680 22 20 64 6F 20 6E 6F 74 20 6F 76 65 72 6C 61 70 20 69 6E 20 6D 65 6D 6F 72 79 20 77 69 74 68 20 " do not overlap in memory with 000056A0 65 6C 65 6D 65 6E 74 73 20 6F 66 20 22 62 2E 22 0D 0A 0D 0A 43 6F 6D 6D 65 6E 74 73 20 20 20 20 elements of "b."♪◙♪◙Comments 000056C0 20 20 20 20 20 20 20 20 20 20 0D 0A 0D 0A 55 73 69 6E 67 20 61 20 6C 6F 61 64 2F 73 74 6F 72 65 ♪◙♪◙Using a load/store 000056E0 20 70 61 72 61 64 69 67 6D 20 77 6F 72 6B 73 20 77 65 6C 6C 20 6F 6E 20 74 68 65 20 50 65 6E 74 paradigm works well on the Pent 00005700 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 20 62 65 63 61 75 73 65 20 69 74 20 65 78 70 6F 73 65 73 ium processor because it exposes 00005720 20 6D 6F 72 65 20 6F 70 70 6F 72 74 75 6E 69 74 69 65 73 20 66 6F 72 20 70 61 69 72 69 6E 67 20 more opportunities for pairing 00005740 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 77 68 65 6E 20 74 68 65 20 69 6E 73 74 72 75 63 74 69 6F instructions when the instructio 00005760 6E 73 20 61 72 65 20 73 63 68 65 64 75 6C 65 64 2E 20 20 49 74 20 64 6F 65 73 20 6E 6F 74 20 68 ns are scheduled. It does not h 00005780 6F 77 65 76 65 72 2C 20 69 6E 63 72 65 61 73 65 20 74 68 65 20 6E 75 6D 62 65 72 20 6F 66 20 63 owever, increase the number of c 000057A0 6C 6F 63 6B 73 2C 20 65 76 65 6E 20 77 69 74 68 6F 75 74 20 73 63 68 65 64 75 6C 69 6E 67 2C 20 locks, even without scheduling, 000057C0 74 68 6F 75 67 68 20 74 68 69 73 20 69 67 6E 6F 72 65 73 20 70 6F 73 73 69 62 6C 65 20 73 65 63 though this ignores possible sec 000057E0 6F 6E 64 61 72 79 20 65 66 66 65 63 74 73 20 73 75 63 68 20 61 73 20 6C 61 72 67 65 72 20 63 6F ondary effects such as larger co 00005800 64 65 20 73 69 7A 65 2E 20 20 20 54 68 69 73 20 63 61 6E 20 6C 65 61 64 20 74 6F 20 69 6E 73 74 de size. This can lead to inst 00005820 72 75 63 74 69 6F 6E 20 63 61 63 68 65 20 6D 69 73 73 65 73 2E 20 20 41 6E 6F 74 68 65 72 20 73 ruction cache misses. Another s 00005840 65 63 6F 6E 64 61 72 79 20 65 66 66 65 63 74 20 69 73 20 74 68 65 20 75 73 65 20 6F 66 20 6D 6F econdary effect is the use of mo 00005860 72 65 20 72 65 67 69 73 74 65 72 73 2C 20 77 68 69 63 68 20 61 72 65 20 61 20 6C 69 6D 69 74 65 re registers, which are a limite 00005880 64 20 72 65 73 6F 75 72 63 65 20 6F 6E 20 74 68 65 73 65 20 70 72 6F 63 65 73 73 6F 72 73 2E 20 d resource on these processors. 000058A0 43 6F 6D 70 69 6C 65 72 20 77 72 69 74 65 72 73 20 6D 61 79 20 77 61 6E 74 20 74 6F 20 70 61 79 Compiler writers may want to pay 000058C0 20 6D 6F 72 65 20 61 74 74 65 6E 74 69 6F 6E 20 74 6F 20 72 65 67 69 73 74 65 72 20 61 6C 6C 6F more attention to register allo 000058E0 63 61 74 69 6F 6E 2E 0D 0A 0D 0A 49 6E 20 74 68 69 73 20 64 6F 63 75 6D 65 6E 74 2C 20 77 65 20 cation.♪◙♪◙In this document, we 00005900 77 69 6C 6C 20 72 65 66 65 72 20 74 6F 20 74 68 69 73 20 61 73 20 22 6C 6F 61 64 2F 73 74 6F 72 will refer to this as "load/stor 00005920 65 22 20 73 74 79 6C 65 20 63 6F 64 65 20 67 65 6E 65 72 61 74 69 6F 6E 2E 0D 0A 0D 0A 0C 34 2E e" style code generation.♪◙♪◙♀4. 00005940 20 43 6F 64 65 20 47 65 6E 65 72 61 74 69 6F 6E 20 53 74 72 61 74 65 67 79 0D 0A 0D 0A 45 76 65 Code Generation Strategy♪◙♪◙Eve 00005960 6E 20 74 68 6F 75 67 68 20 65 61 63 68 20 6D 65 6D 62 65 72 20 6F 66 20 74 68 65 20 49 6E 74 65 n though each member of the Inte 00005980 6C 33 38 36 20 70 72 6F 63 65 73 73 6F 72 20 66 61 6D 69 6C 79 20 68 61 73 20 61 20 64 69 66 66 l386 processor family has a diff 000059A0 65 72 65 6E 74 20 6D 69 63 72 6F 20 61 72 63 68 69 74 65 63 74 75 72 65 20 64 75 65 20 74 6F 0D erent micro architecture due to♪ 000059C0 0A 74 65 63 68 6E 6F 6C 6F 67 79 20 76 65 72 73 75 73 20 69 6D 70 6C 65 6D 65 6E 74 61 74 69 6F ◙technology versus implementatio 000059E0 6E 20 74 72 61 64 65 6F 66 66 73 2C 20 74 68 65 20 64 69 66 66 65 72 65 6E 63 65 73 20 69 6E 64 n tradeoffs, the differences ind 00005A00 75 63 65 64 20 66 65 77 20 63 6F 6E 66 6C 69 63 74 73 20 69 6E 20 74 68 65 20 6F 76 65 72 61 6C uced few conflicts in the overal 00005A20 6C 20 63 6F 64 65 20 6F 70 74 69 6D 69 7A 61 74 69 6F 6E 20 73 74 72 61 74 65 67 79 2E 20 49 6E l code optimization strategy. In 00005A40 20 66 61 63 74 2C 20 74 68 65 72 65 20 69 73 20 61 20 73 65 74 20 6F 66 20 22 62 6C 65 6E 64 65 fact, there is a set of "blende 00005A60 64 22 20 6F 70 74 69 6D 69 7A 61 74 69 6F 6E 73 20 74 68 61 74 20 77 69 6C 6C 20 63 72 65 61 74 d" optimizations that will creat 00005A80 65 20 61 6E 20 6F 70 74 69 6D 61 6C 20 62 69 6E 61 72 79 20 61 63 72 6F 73 73 20 74 68 65 20 65 e an optimal binary across the e 00005AA0 6E 74 69 72 65 20 66 61 6D 69 6C 79 2E 20 54 68 65 20 22 62 6C 65 6E 64 65 64 22 20 6F 70 74 69 ntire family. The "blended" opti 00005AC0 6D 69 7A 61 74 69 6F 6E 73 20 69 6E 63 6C 75 64 65 3A 0D 0A 0D 0A 31 2E 20 4F 70 74 69 6D 69 7A mizations include:♪◙♪◙1. Optimiz 00005AE0 61 74 69 6F 6E 73 20 74 68 61 74 20 62 65 6E 65 66 69 74 20 61 6C 6C 20 6D 65 6D 62 65 72 73 2E ations that benefit all members. 00005B00 0D 0A 0D 0A 32 2E 20 4F 70 74 69 6D 69 7A 61 74 69 6F 6E 73 20 74 68 61 74 20 62 65 6E 65 66 69 ♪◙♪◙2. Optimizations that benefi 00005B20 74 20 6F 6E 65 20 6F 72 20 6D 6F 72 65 20 6D 65 6D 62 65 72 73 20 62 75 74 20 64 6F 20 6E 6F 74 t one or more members but do not 00005B40 20 68 75 72 74 20 74 68 65 20 72 65 6D 61 69 6E 69 6E 67 20 6D 65 6D 62 65 72 73 2E 0D 0A 0D 0A hurt the remaining members.♪◙♪◙ 00005B60 33 2E 20 4F 70 74 69 6D 69 7A 61 74 69 6F 6E 73 20 74 68 61 74 20 62 65 6E 65 66 69 74 20 6F 6E 3. Optimizations that benefit on 00005B80 65 20 6F 72 20 6D 6F 72 65 20 6D 65 6D 62 65 72 73 20 61 20 6C 6F 74 20 62 75 74 20 6F 6E 6C 79 e or more members a lot but only 00005BA0 20 68 75 72 74 20 74 68 65 20 72 65 6D 61 69 6E 69 6E 67 20 6D 65 6D 62 65 72 73 0D 0A 20 20 20 hurt the remaining members♪◙ 00005BC0 20 61 20 6C 69 74 74 6C 65 2E 0D 0A 0D 0A 46 6F 72 20 74 68 6F 73 65 20 6F 70 74 69 6D 69 7A 61 a little.♪◙♪◙For those optimiza 00005BE0 74 69 6F 6E 73 20 74 68 61 74 20 62 65 6E 65 66 69 74 20 6F 6E 6C 79 20 63 65 72 74 61 69 6E 20 tions that benefit only certain 00005C00 6D 65 6D 62 65 72 73 20 62 75 74 20 63 61 75 73 65 20 6E 6F 74 69 63 65 61 62 6C 65 20 64 65 67 members but cause noticeable deg 00005C20 72 61 64 61 74 69 6F 6E 20 74 6F 20 6F 74 68 65 72 73 2C 20 69 74 20 69 73 20 72 65 63 6F 6D 6D radation to others, it is recomm 00005C40 65 6E 64 65 64 20 74 68 61 74 20 74 68 65 79 20 62 65 20 69 6D 70 6C 65 6D 65 6E 74 65 64 20 75 ended that they be implemented u 00005C60 6E 64 65 72 20 73 77 69 74 63 68 65 73 20 61 6E 64 20 6C 65 66 74 20 74 6F 20 74 68 65 20 75 73 nder switches and left to the us 00005C80 65 72 20 74 6F 20 64 65 63 69 64 65 20 77 68 65 74 68 65 72 20 6D 61 78 69 6D 69 7A 69 6E 67 20 er to decide whether maximizing 00005CA0 74 68 65 20 70 65 72 66 6F 72 6D 61 6E 63 65 20 6F 66 20 61 20 73 70 65 63 69 66 69 63 20 70 72 the performance of a specific pr 00005CC0 6F 63 65 73 73 6F 72 20 69 73 20 64 65 73 69 72 61 62 6C 65 2E 0D 0A 0D 0A 0C 35 2E 20 42 6C 65 ocessor is desirable.♪◙♪◙♀5. Ble 00005CE0 6E 64 65 64 20 43 6F 64 65 20 47 65 6E 65 72 61 74 69 6F 6E 20 43 6F 6E 73 69 64 65 72 61 74 69 nded Code Generation Considerati 00005D00 6F 6E 0D 0A 0D 0A 35 2E 31 20 43 68 6F 69 63 65 20 6F 66 20 49 6E 64 65 78 20 56 65 72 73 75 73 on♪◙♪◙5.1 Choice of Index Versus 00005D20 20 42 61 73 65 20 52 65 67 69 73 74 65 72 0D 0A 0D 0A 54 68 65 20 49 6E 74 65 6C 33 38 36 20 61 Base Register♪◙♪◙The Intel386 a 00005D40 6E 64 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 73 20 6E 65 65 64 20 nd the Intel486 processors need 00005D60 61 6E 20 61 64 64 69 74 69 6F 6E 61 6C 20 63 6C 6F 63 6B 20 63 79 63 6C 65 20 74 6F 20 67 65 6E an additional clock cycle to gen 00005D80 65 72 61 74 65 20 61 6E 20 65 66 66 65 63 74 69 76 65 20 61 64 64 72 65 73 73 20 77 68 65 6E 20 erate an effective address when 00005DA0 61 6E 20 69 6E 64 65 78 20 72 65 67 69 73 74 65 72 20 69 73 20 75 73 65 64 2E 20 54 68 65 72 65 an index register is used. There 00005DC0 66 6F 72 65 2C 20 69 66 20 6F 6E 6C 79 20 6F 6E 65 20 69 6E 64 65 78 69 6E 67 20 63 6F 6D 70 6F fore, if only one indexing compo 00005DE0 6E 65 6E 74 20 69 73 20 75 73 65 64 20 28 69 2E 65 2E 2C 20 6E 6F 74 20 62 6F 74 68 20 61 20 62 nent is used (i.e., not both a b 00005E00 61 73 65 20 72 65 67 69 73 74 65 72 20 61 6E 64 20 61 6E 20 69 6E 64 65 78 20 72 65 67 69 73 74 ase register and an index regist 00005E20 65 72 29 20 61 6E 64 20 73 63 61 6C 69 6E 67 20 69 73 20 6E 6F 74 20 6E 65 63 65 73 73 61 72 79 er) and scaling is not necessary 00005E40 2C 20 74 68 65 6E 20 69 74 20 69 73 20 66 61 73 74 65 72 20 74 6F 20 75 73 65 20 74 68 65 20 72 , then it is faster to use the r 00005E60 65 67 69 73 74 65 72 20 61 73 20 61 20 62 61 73 65 20 72 61 74 68 65 72 20 74 68 61 6E 20 61 6E egister as a base rather than an 00005E80 20 69 6E 64 65 78 2E 20 46 6F 72 20 65 78 61 6D 70 6C 65 3A 0D 0A 0D 0A 6D 6F 76 20 20 65 61 78 index. For example:♪◙♪◙mov eax 00005EA0 2C 20 5B 65 73 69 5D 20 20 3B 20 75 73 65 20 65 73 69 20 61 73 20 62 61 73 65 0D 0A 6D 6F 76 20 , [esi] ; use esi as base♪◙mov 00005EC0 20 65 61 78 2C 20 5B 65 73 69 2A 5D 20 3B 20 75 73 65 20 65 73 69 20 61 73 20 69 6E 64 65 78 2C eax, [esi*] ; use esi as index, 00005EE0 20 31 20 63 6C 6F 63 6B 20 70 65 6E 61 6C 74 79 0D 0A 0D 0A 49 74 20 74 61 6B 65 73 20 74 68 65 1 clock penalty♪◙♪◙It takes the 00005F00 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 20 6F 6E 65 20 63 6C 6F 63 6B 20 74 6F 20 Pentium processor one clock to 00005F20 63 61 6C 63 75 6C 61 74 65 20 74 68 65 20 65 66 66 65 63 74 69 76 65 20 61 64 64 72 65 73 73 20 calculate the effective address 00005F40 65 76 65 6E 20 77 68 65 6E 20 61 6E 20 69 6E 64 65 78 20 72 65 67 69 73 74 65 72 20 69 73 20 75 even when an index register is u 00005F60 73 65 64 2E 20 20 48 65 6E 63 65 2C 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 20 69 sed. Hence, Pentium processor i 00005F80 73 20 6E 65 75 74 72 61 6C 20 74 6F 20 74 68 65 20 63 68 6F 69 63 65 20 6F 66 20 69 6E 64 65 78 s neutral to the choice of index 00005FA0 20 76 65 72 73 75 73 20 62 61 73 65 20 72 65 67 69 73 74 65 72 2E 0D 0A 0D 0A 35 2E 32 2E 20 41 versus base register.♪◙♪◙5.2. A 00005FC0 64 64 72 65 73 73 69 6E 67 20 4D 6F 64 65 73 20 61 6E 64 20 52 65 67 69 73 74 65 72 20 55 73 61 ddressing Modes and Register Usa 00005FE0 67 65 0D 0A 0D 0A 31 2E 20 46 6F 72 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 ge♪◙♪◙1. For the Intel486 proces 00006000 73 6F 72 2C 20 77 68 65 6E 20 61 20 72 65 67 69 73 74 65 72 20 69 73 20 75 73 65 64 20 61 73 20 sor, when a register is used as 00006020 74 68 65 20 62 61 73 65 20 63 6F 6D 70 6F 6E 65 6E 74 2C 20 61 6E 20 61 64 64 69 74 69 6F 6E 61 the base component, an additiona 00006040 6C 20 63 6C 6F 63 6B 20 63 79 63 6C 65 20 69 73 20 75 73 65 64 20 69 66 20 74 68 61 74 20 72 65 l clock cycle is used if that re 00006060 67 69 73 74 65 72 20 69 73 20 74 68 65 20 64 65 73 74 69 6E 61 74 69 6F 6E 20 6F 66 20 74 68 65 gister is the destination of the 00006080 20 69 6D 6D 65 64 69 61 74 65 6C 79 20 70 72 65 63 65 64 69 6E 67 20 69 6E 73 74 72 75 63 74 69 immediately preceding instructi 000060A0 6F 6E 20 28 61 73 73 75 6D 69 6E 67 20 61 6C 6C 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 61 72 on (assuming all instructions ar 000060C0 65 20 61 6C 72 65 61 64 79 20 69 6E 20 74 68 65 20 70 72 65 66 65 74 63 68 20 71 75 65 75 65 29 e already in the prefetch queue) 000060E0 2E 20 46 6F 72 20 65 78 61 6D 70 6C 65 3A 0D 0A 0D 0A 61 64 64 20 20 65 73 69 2C 20 65 61 78 20 . For example:♪◙♪◙add esi, eax 00006100 20 20 20 3B 20 65 73 69 20 69 73 20 64 65 73 74 69 6E 61 74 69 6F 6E 20 72 65 67 69 73 74 65 72 ; esi is destination register 00006120 0D 0A 6D 6F 76 20 20 65 61 78 2C 20 5B 65 73 69 5D 20 20 3B 20 65 73 69 20 69 73 20 62 61 73 65 ♪◙mov eax, [esi] ; esi is base 00006140 2C 20 31 20 63 6C 6F 63 6B 20 70 65 6E 61 6C 74 79 0D 0A 0D 0A 53 69 6E 63 65 20 74 68 65 20 50 , 1 clock penalty♪◙♪◙Since the P 00006160 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 20 68 61 73 20 74 77 6F 20 69 6E 74 65 67 65 72 entium processor has two integer 00006180 20 70 69 70 65 6C 69 6E 65 73 20 61 6E 64 20 65 61 63 68 20 70 69 70 65 6C 69 6E 65 20 68 61 73 pipelines and each pipeline has 000061A0 20 61 20 73 69 6D 69 6C 61 72 20 6F 72 67 61 6E 69 7A 61 74 69 6F 6E 20 6F 6E 20 74 68 65 20 49 a similar organization on the I 000061C0 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 2C 20 61 20 72 65 67 69 73 74 65 72 20 75 73 ntel486 processor, a register us 000061E0 65 64 20 61 73 20 74 68 65 20 62 61 73 65 20 6F 72 20 69 6E 64 65 78 20 63 6F 6D 70 6F 6E 65 6E ed as the base or index componen 00006200 74 20 6F 66 20 61 6E 20 65 66 66 65 63 74 69 76 65 20 61 64 64 72 65 73 73 20 63 61 6C 63 75 6C t of an effective address calcul 00006220 61 74 69 6F 6E 20 28 69 6E 20 65 69 74 68 65 72 20 70 69 70 65 29 20 63 61 75 73 65 73 20 61 6E ation (in either pipe) causes an 00006240 20 61 64 64 69 74 69 6F 6E 61 6C 20 63 6C 6F 63 6B 20 63 79 63 6C 65 20 69 66 20 74 68 61 74 20 additional clock cycle if that 00006260 72 65 67 69 73 74 65 72 20 69 73 20 74 68 65 20 64 65 73 74 69 6E 61 74 69 6F 6E 20 6F 66 20 65 register is the destination of e 00006280 69 74 68 65 72 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 66 72 6F 6D 20 74 68 65 20 69 6D 6D 65 64 ither instruction from the immed 000062A0 69 61 74 65 6C 79 20 70 72 65 63 65 64 69 6E 67 20 63 79 63 6C 65 20 28 41 64 64 72 65 73 73 20 iately preceding cycle (Address 000062C0 47 65 6E 65 72 61 74 69 6F 6E 20 49 6E 74 65 72 6C 6F 63 6B 2C 20 28 41 47 49 29 29 2E 20 54 6F Generation Interlock, (AGI)). To 000062E0 20 61 76 6F 69 64 20 74 68 65 20 41 47 49 2C 20 74 68 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 avoid the AGI, the instructions 00006300 20 73 68 6F 75 6C 64 20 62 65 20 73 65 70 61 72 61 74 65 64 20 62 79 20 61 74 20 6C 65 61 73 74 should be separated by at least 00006320 20 6F 6E 65 20 63 79 63 6C 65 20 62 79 20 70 6C 61 63 69 6E 67 20 6F 74 68 65 72 20 69 6E 73 74 one cycle by placing other inst 00006340 72 75 63 74 69 6F 6E 73 20 62 65 74 77 65 65 6E 20 74 68 65 6D 2E 0D 0A 0D 0A 32 2E 20 4E 6F 74 ructions between them.♪◙♪◙2. Not 00006360 65 20 74 68 61 74 20 73 6F 6D 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 68 61 76 65 20 69 6D e that some instructions have im 00006380 70 6C 69 63 69 74 20 72 65 61 64 73 2F 77 72 69 74 65 73 20 74 6F 20 72 65 67 69 73 74 65 72 73 plicit reads/writes to registers 000063A0 2E 20 49 6E 73 74 72 75 63 74 69 6F 6E 73 20 74 68 61 74 20 67 65 6E 65 72 61 74 65 20 61 64 64 . Instructions that generate add 000063C0 72 65 73 73 65 73 20 69 6D 70 6C 69 63 69 74 6C 79 20 74 68 72 6F 75 67 68 20 65 73 70 20 28 70 resses implicitly through esp (p 000063E0 75 73 68 2C 70 6F 70 2F 72 65 74 2F 63 61 6C 6C 29 20 61 6C 73 6F 20 73 75 66 66 65 72 20 66 72 ush,pop/ret/call) also suffer fr 00006400 6F 6D 20 74 68 65 20 41 47 49 20 70 65 6E 61 6C 74 79 2E 0D 0A 0D 0A 45 78 61 6D 70 6C 65 73 3A om the AGI penalty.♪◙♪◙Examples: 00006420 0D 0A 0D 0A 73 75 62 20 20 65 73 70 2C 20 32 34 0D 0A 20 20 20 20 20 20 20 20 3B 20 20 31 20 63 ♪◙♪◙sub esp, 24♪◙ ; 1 c 00006440 79 63 6C 65 20 73 74 61 6C 6C 0D 0A 70 75 73 68 20 65 62 78 0D 0A 0D 0A 0D 0A 6D 6F 76 20 20 65 ycle stall♪◙push ebx♪◙♪◙♪◙mov e 00006460 73 70 2C 20 65 62 70 0D 0A 20 20 20 20 20 20 20 20 3B 20 20 31 20 63 79 63 6C 65 20 73 74 61 6C sp, ebp♪◙ ; 1 cycle stal 00006480 6C 0D 0A 70 6F 70 20 20 65 62 70 0D 0A 0D 0A 50 75 73 68 20 61 6E 64 20 70 6F 70 20 61 6C 73 6F l♪◙pop ebp♪◙♪◙Push and pop also 000064A0 20 69 6D 70 6C 69 63 69 74 6C 79 20 77 72 69 74 65 20 74 6F 20 65 73 70 2E 20 54 68 69 73 2C 20 implicitly write to esp. This, 000064C0 68 6F 77 65 76 65 72 2C 20 64 6F 65 73 20 6E 6F 74 20 63 61 75 73 65 20 61 6E 20 41 47 49 20 77 however, does not cause an AGI w 000064E0 68 65 6E 20 74 68 65 20 6E 65 78 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 61 64 64 72 65 73 73 hen the next instruction address 00006500 65 73 20 74 68 72 6F 75 67 68 20 65 73 70 2E 0D 0A 0D 0A 45 78 61 6D 70 6C 65 3A 0D 0A 0D 0A 70 es through esp.♪◙♪◙Example:♪◙♪◙p 00006520 75 73 68 20 65 64 69 20 20 20 20 20 20 20 20 20 20 3B 20 6E 6F 20 73 74 61 6C 6C 0D 0A 6D 6F 76 ush edi ; no stall♪◙mov 00006540 20 20 65 62 78 2C 20 5B 65 73 70 5D 0D 0A 0D 0A 0C 0D 0A 33 2E 20 4F 6E 20 74 68 65 20 49 6E 74 ebx, [esp]♪◙♪◙♀♪◙3. On the Int 00006560 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 20 74 68 65 72 65 20 69 73 20 61 20 31 2D 63 6C 6F el486 processor there is a 1-clo 00006580 63 6B 20 70 65 6E 61 6C 74 79 20 66 6F 72 20 64 65 63 6F 64 69 6E 67 20 61 6E 20 69 6E 73 74 72 ck penalty for decoding an instr 000065A0 75 63 74 69 6F 6E 20 77 69 74 68 20 65 69 74 68 65 72 20 61 6E 0D 0A 69 6E 64 65 78 20 6F 72 20 uction with either an♪◙index or 000065C0 61 6E 20 69 6D 6D 65 64 69 61 74 65 2D 64 69 73 70 6C 61 63 65 6D 65 6E 74 20 63 6F 6D 62 69 6E an immediate-displacement combin 000065E0 61 74 69 6F 6E 2E 20 4F 6E 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 2C ation. On the Pentium processor, 00006600 20 74 68 65 20 69 6D 6D 65 64 69 61 74 65 2D 64 69 73 70 6C 61 63 65 6D 65 6E 74 20 63 6F 6D 62 the immediate-displacement comb 00006620 69 6E 61 74 69 6F 6E 20 69 73 20 6E 6F 74 20 70 61 69 72 61 62 6C 65 2E 20 57 68 65 6E 20 69 74 ination is not pairable. When it 00006640 20 69 73 20 6E 65 63 65 73 73 61 72 79 20 74 6F 20 75 73 65 20 63 6F 6E 73 74 61 6E 74 73 2C 20 is necessary to use constants, 00006660 69 74 20 77 6F 75 6C 64 20 73 74 69 6C 6C 20 62 65 20 6D 6F 72 65 20 65 66 66 69 63 69 65 6E 74 it would still be more efficient 00006680 20 74 6F 20 75 73 65 20 69 6D 6D 65 64 69 61 74 65 20 64 61 74 61 20 69 6E 73 74 65 61 64 20 6F to use immediate data instead o 000066A0 66 20 6C 6F 61 64 69 6E 67 20 74 68 65 20 63 6F 6E 73 74 61 6E 74 20 69 6E 74 6F 20 61 20 72 65 f loading the constant into a re 000066C0 67 69 73 74 65 72 20 66 69 72 73 74 2E 20 20 48 6F 77 65 76 65 72 2C 20 69 66 20 74 68 65 20 73 gister first. However, if the s 000066E0 61 6D 65 20 69 6D 6D 65 64 69 61 74 65 20 64 61 74 61 20 69 73 20 75 73 65 64 20 6D 6F 72 65 20 ame immediate data is used more 00006700 74 68 61 6E 20 6F 6E 63 65 2C 20 69 74 20 77 6F 75 6C 64 20 62 65 20 66 61 73 74 65 72 20 74 6F than once, it would be faster to 00006720 20 6C 6F 61 64 20 74 68 65 20 63 6F 6E 73 74 61 6E 74 20 69 6E 20 61 20 72 65 67 69 73 74 65 72 load the constant in a register 00006740 20 61 6E 64 20 74 68 65 6E 20 75 73 65 20 74 68 65 20 72 65 67 69 73 74 65 72 20 6D 75 6C 74 69 and then use the register multi 00006760 70 6C 65 20 74 69 6D 65 73 2E 0D 0A 0D 0A 6D 6F 76 20 20 72 65 73 75 6C 74 2C 20 35 35 35 20 09 ple times.♪◙♪◙mov result, 555 ○ 00006780 3B 20 35 35 35 20 69 73 20 69 6D 6D 65 64 69 61 74 65 2C 20 72 65 73 75 6C 74 20 69 73 20 64 69 ; 555 is immediate, result is di 000067A0 73 70 6C 61 63 65 6D 65 6E 74 0D 0A 6D 6F 76 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 73 70 2B splacement♪◙mov dword ptr [esp+ 000067C0 34 5D 2C 20 31 09 3B 20 31 20 20 69 73 20 69 6D 6D 65 64 69 61 74 65 2C 20 20 20 20 20 20 34 20 4], 1○; 1 is immediate, 4 000067E0 69 73 20 64 69 73 70 6C 61 63 65 6D 65 6E 74 0D 0A 0D 0A 34 2E 20 54 68 65 20 49 6E 74 65 6C 34 is displacement♪◙♪◙4. The Intel4 00006800 38 36 20 70 72 6F 63 65 73 73 6F 72 20 68 61 73 20 61 20 31 2D 63 6C 6F 63 6B 20 70 65 6E 61 6C 86 processor has a 1-clock penal 00006820 74 79 20 77 68 65 6E 20 75 73 69 6E 67 20 61 20 72 65 67 69 73 74 65 72 20 69 6D 6D 65 64 69 61 ty when using a register immedia 00006840 74 65 6C 79 20 61 66 74 65 72 20 69 74 73 20 73 75 62 2D 0D 0A 72 65 67 69 73 74 65 72 20 77 61 tely after its sub-♪◙register wa 00006860 73 20 77 72 69 74 74 65 6E 2E 20 20 54 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F s written. The Pentium processo 00006880 72 20 69 73 20 6E 65 75 74 72 61 6C 20 69 6E 20 74 68 69 73 20 72 65 73 70 65 63 74 2E 0D 0A 0D r is neutral in this respect.♪◙♪ 000068A0 0A 45 78 61 6D 70 6C 65 20 28 50 65 6E 74 69 75 6D 20 50 72 6F 63 65 73 73 6F 72 29 3A 0D 0A 0D ◙Example (Pentium Processor):♪◙♪ 000068C0 0A 6D 6F 76 20 20 61 6C 2C 20 20 20 20 20 20 20 30 20 09 3B 20 31 0D 0A 6D 6F 76 20 20 5B 65 62 ◙mov al, 0 ○; 1♪◙mov [eb 000068E0 70 5D 2C 20 65 61 78 20 09 3B 20 32 20 2D 20 4E 6F 20 64 65 6C 61 79 20 6F 6E 20 74 68 65 20 50 p], eax ○; 2 - No delay on the P 00006900 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 0D 0A 0D 0A 45 78 61 6D 70 6C 65 20 28 49 6E 74 entium processor♪◙♪◙Example (Int 00006920 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 29 3A 0D 0A 0D 0A 6D 6F 76 20 20 61 6C 2C 20 20 20 el486 processor):♪◙♪◙mov al, 00006940 20 20 20 20 30 20 09 3B 20 31 0D 0A 09 3B 20 32 0D 0A 6D 6F 76 20 20 5B 65 62 70 5D 2C 20 65 61 0 ○; 1♪◙○; 2♪◙mov [ebp], ea 00006960 78 09 3B 20 33 0D 0A 0D 0A 35 2E 33 20 50 72 65 66 65 74 63 68 20 42 61 6E 64 77 69 64 74 68 0D x○; 3♪◙♪◙5.3 Prefetch Bandwidth♪ 00006980 0A 0D 0A 54 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 20 70 72 65 66 65 74 ◙♪◙The Intel486 processor prefet 000069A0 63 68 20 75 6E 69 74 20 77 69 6C 6C 20 61 63 63 65 73 73 20 74 68 65 20 6F 6E 2D 63 68 69 70 20 ch unit will access the on-chip 000069C0 63 61 63 68 65 20 74 6F 20 66 69 6C 6C 20 74 68 65 20 70 72 65 66 65 74 63 68 20 71 75 65 75 65 cache to fill the prefetch queue 000069E0 20 77 68 65 6E 65 76 65 72 20 74 68 65 20 63 61 63 68 65 20 69 73 20 69 64 6C 65 20 61 6E 64 20 whenever the cache is idle and 00006A00 74 68 65 72 65 20 69 73 20 65 6E 6F 75 67 68 20 72 6F 6F 6D 20 69 6E 20 74 68 65 20 71 75 65 75 there is enough room in the queu 00006A20 65 20 66 6F 72 20 61 6E 6F 74 68 65 72 20 63 61 63 68 65 20 6C 69 6E 65 20 28 31 36 20 62 79 74 e for another cache line (16 byt 00006A40 65 73 29 2E 20 49 66 20 74 68 65 20 70 72 65 66 65 74 63 68 20 71 75 65 75 65 20 62 65 63 6F 6D es). If the prefetch queue becom 00006A60 65 73 20 65 6D 70 74 79 2C 20 69 74 20 63 61 6E 20 74 61 6B 65 20 75 70 20 74 6F 20 74 68 72 65 es empty, it can take up to thre 00006A80 65 20 61 64 64 69 74 69 6F 6E 61 6C 20 63 6C 6F 63 6B 73 20 74 6F 20 73 74 61 72 74 20 74 68 65 e additional clocks to start the 00006AA0 20 6E 65 78 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 2E 20 54 68 65 20 70 72 65 66 65 74 63 68 20 next instruction. The prefetch 00006AC0 71 75 65 75 65 20 69 73 20 33 32 20 62 79 74 65 73 20 69 6E 20 73 69 7A 65 20 28 32 20 63 61 63 queue is 32 bytes in size (2 cac 00006AE0 68 65 20 6C 69 6E 65 73 29 2E 0D 0A 0D 0A 42 65 63 61 75 73 65 20 64 61 74 61 20 61 63 63 65 73 he lines).♪◙♪◙Because data acces 00006B00 73 65 73 20 61 6C 77 61 79 73 20 68 61 76 65 20 70 72 69 6F 72 69 74 79 20 6F 76 65 72 20 70 72 ses always have priority over pr 00006B20 65 66 65 74 63 68 20 72 65 71 75 65 73 74 73 2C 20 6B 65 65 70 69 6E 67 20 74 68 65 20 63 61 63 efetch requests, keeping the cac 00006B40 68 65 20 62 75 73 79 20 77 69 74 68 20 64 61 74 61 20 61 63 63 65 73 73 65 73 20 63 61 6E 20 6C he busy with data accesses can l 00006B60 6F 63 6B 20 6F 75 74 20 74 68 65 20 70 72 65 66 65 74 63 68 20 75 6E 69 74 2E 20 41 73 20 61 20 ock out the prefetch unit. As a 00006B80 72 65 73 75 6C 74 2C 20 6F 70 74 69 6D 69 7A 65 64 20 63 6F 64 65 20 73 68 6F 75 6C 64 20 61 76 result, optimized code should av 00006BA0 6F 69 64 20 66 6F 75 72 20 63 6F 6E 73 65 63 75 74 69 76 65 20 6D 65 6D 6F 72 79 20 69 6E 73 74 oid four consecutive memory inst 00006BC0 72 75 63 74 69 6F 6E 73 2E 0D 0A 0D 0A 49 74 20 69 73 20 69 6D 70 6F 72 74 61 6E 74 20 74 6F 20 ructions.♪◙♪◙It is important to 00006BE0 61 72 72 61 6E 67 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 73 6F 20 74 68 61 74 20 74 68 65 arrange instructions so that the 00006C00 20 6D 65 6D 6F 72 79 20 62 75 73 20 69 73 20 6E 6F 74 20 75 73 65 64 20 63 6F 6E 74 69 6E 75 6F memory bus is not used continuo 00006C20 75 73 6C 79 20 62 79 20 61 20 73 65 72 69 65 73 20 6F 66 20 6D 65 6D 6F 72 79 2D 72 65 66 65 72 usly by a series of memory-refer 00006C40 65 6E 63 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 2E 20 54 68 65 20 69 6E 73 74 72 75 63 74 69 ence instructions. The instructi 00006C60 6F 6E 73 20 73 68 6F 75 6C 64 20 62 65 20 72 65 61 72 72 61 6E 67 65 64 20 73 6F 20 74 68 61 74 ons should be rearranged so that 00006C80 20 74 68 65 72 65 20 69 73 20 61 20 6E 6F 6E 2D 6D 65 6D 6F 72 79 20 72 65 66 65 72 65 6E 63 69 there is a non-memory referenci 00006CA0 6E 67 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 28 73 75 63 68 20 61 73 20 61 20 72 65 67 69 73 74 ng instruction (such as a regist 00006CC0 65 72 20 69 6E 73 74 72 75 63 74 69 6F 6E 29 20 61 74 20 6C 65 61 73 74 20 74 77 6F 20 63 6C 6F er instruction) at least two clo 00006CE0 63 6B 73 20 62 65 66 6F 72 65 20 74 68 65 20 70 72 65 66 65 74 63 68 20 71 75 65 75 65 20 62 65 cks before the prefetch queue be 00006D00 63 6F 6D 65 73 20 65 78 68 61 75 73 74 65 64 2E 20 54 68 69 73 20 77 69 6C 6C 20 61 6C 6C 6F 77 comes exhausted. This will allow 00006D20 20 74 68 65 20 70 72 65 66 65 74 63 68 20 75 6E 69 74 20 74 6F 20 74 72 61 6E 73 66 65 72 20 61 the prefetch unit to transfer a 00006D40 20 63 61 63 68 65 20 6C 69 6E 65 20 69 6E 74 6F 20 74 68 65 20 71 75 65 75 65 2E 0D 0A 0D 0A 53 cache line into the queue.♪◙♪◙S 00006D60 75 63 68 20 61 72 72 61 6E 67 65 6D 65 6E 74 20 6F 66 20 74 68 65 20 69 6E 73 74 72 75 63 74 69 uch arrangement of the instructi 00006D80 6F 6E 73 20 77 69 6C 6C 20 6E 6F 74 20 61 66 66 65 63 74 20 74 68 65 20 70 65 72 66 6F 72 6D 61 ons will not affect the performa 00006DA0 6E 63 65 20 6F 66 20 74 68 65 20 49 6E 74 65 6C 33 38 36 20 61 6E 64 20 50 65 6E 74 69 75 6D 0D nce of the Intel386 and Pentium♪ 00006DC0 0A 70 72 6F 63 65 73 73 6F 72 73 2E 0D 0A 0D 0A 49 6E 20 67 65 6E 65 72 61 6C 2C 20 69 74 20 69 ◙processors.♪◙♪◙In general, it i 00006DE0 73 20 64 69 66 66 69 63 75 6C 74 20 66 6F 72 20 61 20 63 6F 6D 70 69 6C 65 72 20 74 6F 20 6D 6F s difficult for a compiler to mo 00006E00 64 65 6C 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 65 66 65 74 63 68 20 62 75 66 66 65 72 del the Intel486 prefetch buffer 00006E20 20 62 65 68 61 76 69 6F 72 2E 20 41 20 73 65 71 75 65 6E 63 65 20 6F 66 20 66 6F 75 72 20 63 6F behavior. A sequence of four co 00006E40 6E 73 65 63 75 74 69 76 65 20 6D 65 6D 6F 72 79 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 77 69 nsecutive memory instructions wi 00006E60 74 68 6F 75 74 20 73 74 61 6C 6C 73 20 28 69 2E 65 2E 2C 20 69 6E 64 65 78 20 70 65 6E 61 6C 74 thout stalls (i.e., index penalt 00006E80 79 29 20 77 69 6C 6C 20 70 72 6F 62 61 62 6C 79 20 73 74 61 6C 6C 20 62 65 63 61 75 73 65 20 6F y) will probably stall because o 00006EA0 66 20 74 68 65 20 70 72 65 66 65 74 63 68 20 62 75 66 66 65 72 73 20 62 65 69 6E 67 20 65 78 68 f the prefetch buffers being exh 00006EC0 61 75 73 74 65 64 2E 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 35 2E 34 20 41 6C 69 austed.♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙♪◙5.4 Ali 00006EE0 67 6E 6D 65 6E 74 0D 0A 0D 0A 35 2E 34 2E 31 20 43 6F 64 65 20 20 20 20 20 20 20 20 20 20 20 20 gnment♪◙♪◙5.4.1 Code 00006F00 20 20 20 20 20 20 20 0D 0A 20 20 20 20 20 20 20 0D 0A 54 68 65 20 49 6E 74 65 6C 34 38 36 20 70 ♪◙ ♪◙The Intel486 p 00006F20 72 6F 63 65 73 73 6F 72 20 68 61 73 20 61 20 63 61 63 68 65 20 6C 69 6E 65 20 73 69 7A 65 20 6F rocessor has a cache line size o 00006F40 66 20 31 36 20 62 79 74 65 73 20 61 6E 64 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 f 16 bytes and the Pentium proce 00006F60 73 73 6F 72 20 68 61 73 20 61 20 63 61 63 68 65 20 6C 69 6E 65 20 73 69 7A 65 20 6F 66 20 33 32 ssor has a cache line size of 32 00006F80 20 62 79 74 65 73 2E 20 53 69 6E 63 65 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 bytes. Since the Intel486 proce 00006FA0 73 73 6F 72 20 68 61 73 20 6F 6E 6C 79 20 74 77 6F 20 70 72 65 66 65 74 63 68 20 62 75 66 66 65 ssor has only two prefetch buffe 00006FC0 72 73 20 28 31 36 20 62 79 74 65 73 20 65 61 63 68 29 2C 20 63 6F 64 65 20 61 6C 69 67 6E 6D 65 rs (16 bytes each), code alignme 00006FE0 6E 74 20 68 61 73 20 61 20 64 69 72 65 63 74 20 69 6D 70 61 63 74 20 6F 6E 20 49 6E 74 65 6C 34 nt has a direct impact on Intel4 00007000 38 36 20 70 72 6F 63 65 73 73 6F 72 20 70 65 72 66 6F 72 6D 61 6E 63 65 20 61 73 20 61 20 72 65 86 processor performance as a re 00007020 73 75 6C 74 20 6F 66 20 74 68 65 20 70 72 65 66 65 74 63 68 20 62 75 66 66 65 72 20 65 66 66 69 sult of the prefetch buffer effi 00007040 63 69 65 6E 63 79 2E 20 43 6F 64 65 20 61 6C 69 67 6E 6D 65 6E 74 20 68 61 73 20 6C 69 74 74 6C ciency. Code alignment has littl 00007060 65 20 65 66 66 65 63 74 20 6F 6E 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F e effect on the Pentium processo 00007080 72 20 70 65 72 66 6F 72 6D 61 6E 63 65 20 62 65 63 61 75 73 65 20 6F 66 20 69 74 73 20 61 62 69 r performance because of its abi 000070A0 6C 69 74 79 20 74 6F 20 70 72 65 66 65 74 63 68 20 61 63 72 6F 73 73 20 61 20 63 61 63 68 65 20 lity to prefetch across a cache 000070C0 6C 69 6E 65 20 62 6F 75 6E 64 61 72 79 20 77 69 74 68 20 6E 6F 20 70 65 6E 61 6C 74 79 2E 20 20 line boundary with no penalty. 000070E0 54 68 65 20 49 6E 74 65 6C 33 38 36 20 70 72 6F 63 65 73 73 6F 72 20 77 69 74 68 20 6E 6F 20 6F The Intel386 processor with no o 00007100 6E 2D 63 68 69 70 20 63 61 63 68 65 20 61 6E 64 20 61 20 64 65 63 6F 75 70 6C 65 64 20 70 72 65 n-chip cache and a decoupled pre 00007120 66 65 74 63 68 20 75 6E 69 74 20 69 73 20 6E 6F 74 20 73 65 6E 73 69 74 69 76 65 20 74 6F 20 63 fetch unit is not sensitive to c 00007140 6F 64 65 20 61 6C 69 67 6E 6D 65 6E 74 2E 20 46 6F 72 20 6F 70 74 69 6D 61 6C 20 70 65 72 66 6F ode alignment. For optimal perfo 00007160 72 6D 61 6E 63 65 20 61 63 72 6F 73 73 20 74 68 65 20 66 61 6D 69 6C 79 2C 20 69 74 20 69 73 20 rmance across the family, it is 00007180 72 65 63 6F 6D 6D 65 6E 64 65 64 20 74 68 61 74 20 6C 61 62 65 6C 73 20 62 65 20 61 6C 69 67 6E recommended that labels be align 000071A0 65 64 20 74 6F 20 74 68 65 20 6E 65 78 74 20 30 4D 4F 44 31 36 20 77 68 65 6E 20 69 74 20 69 73 ed to the next 0MOD16 when it is 000071C0 20 6C 65 73 73 20 74 68 61 6E 20 38 20 62 79 74 65 73 20 61 77 61 79 20 66 72 6F 6D 20 74 68 61 less than 8 bytes away from tha 000071E0 74 20 62 6F 75 6E 64 61 72 79 2E 0D 0A 0D 0A 35 2E 34 2E 32 2E 20 44 61 74 61 0D 0A 0D 0A 41 20 t boundary.♪◙♪◙5.4.2. Data♪◙♪◙A 00007200 6D 69 73 61 6C 69 67 6E 65 64 20 61 63 63 65 73 73 20 69 6E 20 74 68 65 20 64 61 74 61 20 63 61 misaligned access in the data ca 00007220 63 68 65 20 63 6F 73 74 73 20 61 74 20 6C 65 61 73 74 20 61 6E 20 65 78 74 72 61 20 33 20 63 79 che costs at least an extra 3 cy 00007240 63 6C 65 73 20 6F 6E 20 62 6F 74 68 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 61 6E 64 20 50 65 cles on both the Intel486 and Pe 00007260 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 2E 0D 0A 0D 0A 35 2E 34 2E 33 2E 20 20 32 2D 62 79 ntium processor.♪◙♪◙5.4.3. 2-by 00007280 74 65 20 44 61 74 61 3A 20 41 20 32 2D 62 79 74 65 20 6F 62 6A 65 63 74 20 73 68 6F 75 6C 64 20 te Data: A 2-byte object should 000072A0 62 65 20 66 75 6C 6C 79 20 63 6F 6E 74 61 69 6E 65 64 20 77 69 74 68 69 6E 20 61 6E 20 61 6C 69 be fully contained within an ali 000072C0 67 6E 65 64 20 34 2D 62 79 74 65 20 77 6F 72 64 20 28 69 2E 65 2E 2C 20 69 74 73 20 62 69 6E 61 gned 4-byte word (i.e., its bina 000072E0 72 79 20 61 64 64 72 65 73 73 20 73 68 6F 75 6C 64 20 62 65 20 78 78 78 78 30 30 2C 20 78 78 78 ry address should be xxxx00, xxx 00007300 78 30 31 2C 20 78 78 78 78 31 30 2C 20 62 75 74 20 6E 6F 74 20 78 78 78 78 31 31 29 2E 0D 0A 0D x01, xxxx10, but not xxxx11).♪◙♪ 00007320 0A 35 2E 34 2E 34 2E 20 20 34 2D 62 79 74 65 20 44 61 74 61 3A 20 54 68 65 20 61 6C 69 67 6E 6D ◙5.4.4. 4-byte Data: The alignm 00007340 65 6E 74 20 6F 66 20 34 2D 62 79 74 65 20 6F 62 6A 65 63 74 20 73 68 6F 75 6C 64 20 62 65 20 6F ent of 4-byte object should be o 00007360 6E 20 61 20 34 2D 62 79 74 65 20 62 6F 75 6E 64 61 72 79 2E 0D 0A 0D 0A 35 2E 34 2E 35 2E 20 20 n a 4-byte boundary.♪◙♪◙5.4.5. 00007380 38 2D 62 79 74 65 20 44 61 74 61 3A 20 20 41 6E 20 38 2D 62 79 74 65 20 64 61 74 75 6D 20 28 36 8-byte Data: An 8-byte datum (6 000073A0 34 2D 62 69 74 2C 20 65 2E 67 2E 2C 20 64 6F 75 62 6C 65 2D 70 72 65 63 69 73 69 6F 6E 20 72 65 4-bit, e.g., double-precision re 000073C0 61 6C 73 29 20 73 68 6F 75 6C 64 20 62 65 20 61 6C 69 67 6E 65 64 20 6F 6E 20 61 6E 20 38 2D 62 als) should be aligned on an 8-b 000073E0 79 74 65 20 62 6F 75 6E 64 61 72 79 2E 0D 0A 0D 0A 35 2E 35 20 50 72 65 66 69 78 65 64 20 4F 70 yte boundary.♪◙♪◙5.5 Prefixed Op 00007400 63 6F 64 65 73 0D 0A 0D 0A 4F 6E 20 74 68 65 20 49 6E 74 65 6C 33 38 36 20 70 72 6F 63 65 73 73 codes♪◙♪◙On the Intel386 process 00007420 6F 72 20 61 6E 64 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 2C 20 61 or and the Intel486 processor, a 00007440 6C 6C 20 70 72 65 66 69 78 20 6F 70 63 6F 64 65 73 20 72 65 71 75 69 72 65 20 61 6E 20 61 64 64 ll prefix opcodes require an add 00007460 69 74 69 6F 6E 61 6C 20 63 6C 6F 63 6B 20 74 6F 20 64 65 63 6F 64 65 2E 20 4F 6E 20 74 68 65 20 itional clock to decode. On the 00007480 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 2C 20 61 6E 20 69 6E 73 74 72 75 63 74 69 6F Pentium processor, an instructio 000074A0 6E 20 77 69 74 68 20 61 20 70 72 65 66 69 78 20 69 73 20 70 61 69 72 61 62 6C 65 20 69 6E 20 74 n with a prefix is pairable in t 000074C0 68 65 20 55 20 70 69 70 65 20 28 50 55 29 20 69 66 20 74 68 65 20 69 6E 73 74 72 75 63 74 69 6F he U pipe (PU) if the instructio 000074E0 6E 20 28 77 69 74 68 6F 75 74 20 74 68 65 20 70 72 65 66 69 78 29 20 69 73 20 70 61 69 72 61 62 n (without the prefix) is pairab 00007500 6C 65 20 69 6E 20 62 6F 74 68 20 70 69 70 65 73 20 28 55 56 29 20 6F 72 20 69 6E 20 74 68 65 20 le in both pipes (UV) or in the 00007520 55 20 70 69 70 65 20 28 50 55 29 2E 20 54 68 69 73 20 69 73 20 61 20 73 70 65 63 69 61 6C 20 63 U pipe (PU). This is a special c 00007540 61 73 65 20 6F 66 20 70 61 69 72 69 6E 67 2E 20 54 68 65 20 70 72 65 66 69 78 65 73 20 61 72 65 ase of pairing. The prefixes are 00007560 20 69 73 73 75 65 64 20 74 6F 20 74 68 65 20 55 20 70 69 70 65 20 61 6E 64 20 67 65 74 20 64 65 issued to the U pipe and get de 00007580 63 6F 64 65 64 20 69 6E 20 6F 6E 65 20 63 79 63 6C 65 20 66 6F 72 20 65 61 63 68 20 70 72 65 66 coded in one cycle for each pref 000075A0 69 78 20 61 6E 64 20 74 68 65 6E 20 74 68 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 69 73 20 69 ix and then the instruction is i 000075C0 73 73 75 65 64 20 74 6F 20 74 68 65 20 55 20 70 69 70 65 20 61 6E 64 20 6D 61 79 20 62 65 20 70 ssued to the U pipe and may be p 000075E0 61 69 72 65 64 2E 0D 0A 0D 0A 41 6C 6C 20 74 68 65 73 65 20 70 72 65 66 69 78 65 73 3A 20 6C 6F aired.♪◙♪◙All these prefixes: lo 00007600 63 6B 2C 20 73 65 67 6D 65 6E 74 20 6F 76 65 72 72 69 64 65 2C 20 61 64 64 72 65 73 73 20 73 69 ck, segment override, address si 00007620 7A 65 2C 20 73 65 63 6F 6E 64 20 6F 70 63 6F 64 65 20 6D 61 70 20 28 4F 66 29 2C 20 61 6E 64 20 ze, second opcode map (Of), and 00007640 6F 70 65 72 61 6E 64 20 73 69 7A 65 20 62 65 6C 6F 6E 67 20 74 6F 20 74 68 69 73 20 67 72 6F 75 operand size belong to this grou 00007660 70 2E 20 4E 6F 74 65 20 74 68 61 74 20 74 68 69 73 20 69 6E 63 6C 75 64 65 73 20 61 6C 6C 20 74 p. Note that this includes all t 00007680 68 65 20 31 36 20 62 69 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 77 68 65 6E 20 65 78 65 63 he 16 bit instructions when exec 000076A0 75 74 69 6E 67 20 69 6E 20 33 32 2D 62 69 74 20 6D 6F 64 65 20 62 65 63 61 75 73 65 20 61 6E 20 uting in 32-bit mode because an 000076C0 6F 70 65 72 61 6E 64 20 73 69 7A 65 20 70 72 65 66 69 78 20 69 73 20 72 65 71 75 69 72 65 64 20 operand size prefix is required 000076E0 28 65 2E 67 2E 2C 20 6D 6F 76 20 77 6F 72 64 20 70 74 72 20 5B 2E 2E 5D 2C 20 61 64 64 20 77 6F (e.g., mov word ptr [..], add wo 00007700 72 64 20 70 74 72 20 5B 2E 2E 5D 2C 20 2E 2E 2E 29 0D 0A 0D 0A 54 68 65 20 6E 65 61 72 20 6A 63 rd ptr [..], ...)♪◙♪◙The near jc 00007720 63 20 70 72 65 66 69 78 20 62 65 68 61 76 65 73 20 64 69 66 66 65 72 65 6E 74 6C 79 3B 20 69 74 c prefix behaves differently; it 00007740 20 64 6F 65 73 20 6E 6F 74 20 74 61 6B 65 20 61 6E 20 65 78 74 72 61 20 63 79 63 6C 65 20 74 6F does not take an extra cycle to 00007760 20 64 65 63 6F 64 65 20 61 6E 64 20 62 65 6C 6F 6E 67 73 20 74 6F 20 50 56 20 67 72 6F 75 70 2E decode and belongs to PV group. 00007780 20 20 4F 74 68 65 72 20 30 66 20 6F 70 63 6F 64 65 73 20 62 65 68 61 76 65 20 61 73 20 6E 6F 72 Other 0f opcodes behave as nor 000077A0 6D 61 6C 20 70 72 65 66 69 78 65 64 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 2E 20 46 6F 72 20 6F mal prefixed instructions. For o 000077C0 70 74 69 6D 69 7A 65 64 20 63 6F 64 65 2C 20 70 72 65 66 69 78 65 64 20 6F 70 63 6F 64 65 73 20 ptimized code, prefixed opcodes 000077E0 73 68 6F 75 6C 64 20 62 65 20 61 76 6F 69 64 65 64 2E 0D 0A 0D 0A 57 68 65 6E 20 70 72 65 66 69 should be avoided.♪◙♪◙When prefi 00007800 78 65 64 20 6F 70 63 6F 64 65 73 20 68 61 76 65 20 74 6F 20 62 65 20 75 73 65 64 2C 20 74 68 65 xed opcodes have to be used, the 00007820 72 65 20 61 72 65 20 74 77 6F 20 63 61 73 65 73 20 69 6E 20 77 68 69 63 68 20 6F 76 65 72 6C 61 re are two cases in which overla 00007840 70 20 63 61 6E 20 62 65 20 61 63 68 69 65 76 65 64 20 62 65 74 77 65 65 6E 20 74 68 65 20 65 78 p can be achieved between the ex 00007860 74 72 61 20 63 6C 6F 63 6B 20 69 74 20 74 61 6B 65 73 20 74 6F 20 64 65 63 6F 64 65 20 61 20 70 tra clock it takes to decode a p 00007880 72 65 66 69 78 20 61 6E 64 20 61 20 63 79 63 6C 65 20 75 73 65 64 20 62 79 20 74 68 65 20 70 72 refix and a cycle used by the pr 000078A0 65 76 69 6F 75 73 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 65 78 65 63 75 74 69 6E 67 20 69 6E 20 evious instruction executing in 000078C0 74 68 65 20 73 61 6D 65 20 70 69 70 65 3A 0D 0A 0D 0A 31 2E 20 54 68 65 20 6F 6E 65 2D 63 79 63 the same pipe:♪◙♪◙1. The one-cyc 000078E0 6C 65 20 70 65 6E 61 6C 74 79 20 66 72 6F 6D 20 75 73 69 6E 67 20 74 68 65 20 72 65 73 75 6C 74 le penalty from using the result 00007900 20 72 65 67 69 73 74 65 72 20 6F 66 20 61 20 70 72 65 76 69 6F 75 73 20 69 6E 73 74 72 75 63 74 register of a previous instruct 00007920 69 6F 6E 20 61 73 20 61 20 62 61 73 65 20 6F 72 20 69 6E 64 65 78 20 28 41 47 49 29 2E 0D 0A 0D ion as a base or index (AGI).♪◙♪ 00007940 0A 32 2E 20 54 68 65 20 6C 61 73 74 20 63 79 63 6C 65 20 6F 66 20 61 20 70 72 65 63 65 64 69 6E ◙2. The last cycle of a precedin 00007960 67 20 6D 75 6C 74 69 2D 63 79 63 6C 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 2E 0D 0A 0D 0A 0D 0A g multi-cycle instruction.♪◙♪◙♪◙ 00007980 0D 0A 0D 0A 0D 0A 35 2E 36 20 49 6E 74 65 67 65 72 20 49 6E 73 74 72 75 63 74 69 6F 6E 20 53 63 ♪◙♪◙♪◙5.6 Integer Instruction Sc 000079A0 68 65 64 75 6C 69 6E 67 0D 0A 0D 0A 49 6E 73 74 72 75 63 74 69 6F 6E 20 73 63 68 65 64 75 6C 69 heduling♪◙♪◙Instruction scheduli 000079C0 6E 67 20 69 73 20 74 68 65 20 70 72 6F 63 65 73 73 20 6F 66 20 72 65 6F 72 64 65 72 69 6E 67 20 ng is the process of reordering 000079E0 74 68 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 69 6E 20 61 20 70 72 6F 67 72 61 6D 20 74 6F the instructions in a program to 00007A00 20 61 76 6F 69 64 20 73 74 61 6C 6C 73 0D 0A 61 6E 64 20 64 65 6C 61 79 73 20 77 68 69 6C 65 20 avoid stalls♪◙and delays while 00007A20 6D 61 69 6E 74 61 69 6E 69 6E 67 20 74 68 65 20 73 65 6D 61 6E 74 69 63 73 20 6F 66 20 74 68 65 maintaining the semantics of the 00007A40 20 67 65 6E 65 72 61 74 65 64 20 63 6F 64 65 2E 0D 0A 0D 0A 53 63 68 65 64 75 6C 69 6E 67 20 6F generated code.♪◙♪◙Scheduling o 00007A60 66 20 69 6E 74 65 67 65 72 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 68 61 73 20 74 77 6F 20 70 f integer instructions has two p 00007A80 75 72 70 6F 73 65 73 3A 0D 0A 0D 0A 31 2E 20 20 45 6C 69 6D 69 6E 61 74 65 20 73 74 61 6C 6C 73 urposes:♪◙♪◙1. Eliminate stalls 00007AA0 20 69 6E 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 69 70 65 6C 69 6E 65 20 61 6E 64 20 65 61 in the Intel486 pipeline and ea 00007AC0 63 68 20 70 69 70 65 20 6F 66 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 ch pipe of the Pentium processor 00007AE0 2E 0D 0A 0D 0A 54 68 65 72 65 20 61 72 65 20 73 6F 6D 65 20 63 6F 6E 64 69 74 69 6F 6E 73 20 77 .♪◙♪◙There are some conditions w 00007B00 68 65 72 65 20 70 69 70 65 20 73 74 61 6C 6C 73 20 61 72 65 20 65 6E 63 6F 75 6E 74 65 72 65 64 here pipe stalls are encountered 00007B20 2E 20 54 68 65 20 67 65 6E 65 72 61 6C 20 67 75 69 64 65 6C 69 6E 65 20 69 73 20 74 6F 20 66 69 . The general guideline is to fi 00007B40 6E 64 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 74 68 61 74 20 63 61 6E 20 62 65 20 69 6E 73 65 nd instructions that can be inse 00007B60 72 74 65 64 20 62 65 74 77 65 65 6E 20 74 68 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 74 68 rted between the instructions th 00007B80 61 74 20 63 61 75 73 65 20 61 20 73 74 61 6C 6C 2E 20 53 69 6E 63 65 20 6D 6F 73 74 20 6F 66 20 at cause a stall. Since most of 00007BA0 74 68 65 20 63 6F 6D 6D 6F 6E 6C 79 20 75 73 65 64 20 69 6E 74 65 67 65 72 20 69 6E 73 74 72 75 the commonly used integer instru 00007BC0 63 74 69 6F 6E 73 20 74 61 6B 65 20 6F 6E 6C 79 20 6F 6E 65 20 63 6C 6F 63 6B 2C 20 74 68 65 72 ctions take only one clock, ther 00007BE0 65 20 69 73 20 6E 6F 74 20 6D 75 63 68 20 6E 65 65 64 20 74 6F 20 68 69 64 65 20 6C 61 74 65 6E e is not much need to hide laten 00007C00 63 69 65 73 2E 20 54 68 65 20 6D 6F 73 74 20 63 6F 6D 6D 6F 6E 20 64 65 6C 61 79 73 20 77 68 69 cies. The most common delays whi 00007C20 63 68 20 63 61 6E 20 62 65 20 61 76 6F 69 64 65 64 20 74 68 72 6F 75 67 68 20 73 63 68 65 64 75 ch can be avoided through schedu 00007C40 6C 69 6E 67 20 61 72 65 20 41 47 49 20 27 73 2E 0D 0A 0D 0A 32 2E 20 20 43 72 65 61 74 65 20 70 ling are AGI 's.♪◙♪◙2. Create p 00007C60 61 69 72 73 20 66 6F 72 20 6D 61 78 69 6D 75 6D 20 74 68 72 6F 75 67 68 70 75 74 20 66 72 6F 6D airs for maximum throughput from 00007C80 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 27 73 20 64 75 61 6C 20 70 69 the Pentium processor's dual pi 00007CA0 70 65 20 61 72 63 68 69 74 65 63 74 75 72 65 3A 0D 0A 0D 0A 54 68 65 20 50 65 6E 74 69 75 6D 20 pe architecture:♪◙♪◙The Pentium 00007CC0 70 72 6F 63 65 73 73 6F 72 20 63 61 6E 20 69 73 73 75 65 20 74 77 6F 20 69 6E 73 74 72 75 63 74 processor can issue two instruct 00007CE0 69 6F 6E 73 20 66 6F 72 20 65 78 65 63 75 74 69 6F 6E 20 73 69 6D 75 6C 74 61 6E 65 6F 75 73 6C ions for execution simultaneousl 00007D00 79 2E 20 54 68 69 73 20 69 73 20 63 61 6C 6C 65 64 20 70 61 69 72 69 6E 67 2E 20 54 68 65 72 65 y. This is called pairing. There 00007D20 20 61 72 65 20 6C 69 6D 69 74 61 74 69 6F 6E 73 20 6F 6E 20 77 68 69 63 68 20 74 77 6F 20 69 6E are limitations on which two in 00007D40 73 74 72 75 63 74 69 6F 6E 73 20 63 61 6E 20 62 65 20 70 61 69 72 65 64 20 61 6E 64 20 73 6F 6D structions can be paired and som 00007D60 65 20 70 61 69 72 73 2C 20 65 76 65 6E 20 77 68 65 6E 20 69 73 73 75 65 64 2C 20 77 69 6C 6C 20 e pairs, even when issued, will 00007D80 6E 6F 74 20 65 78 65 63 75 74 65 20 69 6E 20 70 61 72 61 6C 6C 65 6C 2E 20 50 61 69 72 69 6E 67 not execute in parallel. Pairing 00007DA0 20 64 65 74 61 69 6C 73 20 61 72 65 20 64 65 73 63 72 69 62 65 64 20 69 6E 20 66 6F 6C 6C 6F 77 details are described in follow 00007DC0 69 6E 67 20 73 65 63 74 69 6F 6E 73 2E 20 20 4D 6F 72 65 20 69 6E 66 6F 72 6D 61 74 69 6F 6E 20 ing sections. More information 00007DE0 61 62 6F 75 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 70 61 69 72 61 62 69 6C 69 74 79 20 63 61 about instruction pairability ca 00007E00 6E 20 62 65 20 66 6F 75 6E 64 20 69 6E 20 41 70 70 65 6E 64 69 78 20 41 2E 0D 0A 0D 0A 52 65 6F n be found in Appendix A.♪◙♪◙Reo 00007E20 72 64 65 72 69 6E 67 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 73 68 6F 75 6C 64 20 62 65 20 64 rdering instructions should be d 00007E40 6F 6E 65 20 69 6E 20 6F 72 64 65 72 20 74 6F 20 69 6E 63 72 65 61 73 65 20 74 68 65 20 70 6F 73 one in order to increase the pos 00007E60 73 69 62 69 6C 69 74 79 20 6F 66 20 69 73 73 75 69 6E 67 20 74 77 6F 20 69 6E 73 74 72 75 63 74 sibility of issuing two instruct 00007E80 69 6F 6E 73 20 73 69 6D 75 6C 74 61 6E 65 6F 75 73 6C 79 2E 20 20 44 65 70 65 6E 64 65 6E 74 20 ions simultaneously. Dependent 00007EA0 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 73 68 6F 75 6C 64 20 62 65 20 73 65 70 61 72 61 74 65 64 instructions should be separated 00007EC0 20 62 79 20 61 74 20 6C 65 61 73 74 20 6F 6E 65 20 6F 74 68 65 72 20 69 6E 73 74 72 75 63 74 69 by at least one other instructi 00007EE0 6F 6E 2E 20 53 63 68 65 64 75 6C 69 6E 67 20 66 6F 72 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 on. Scheduling for the Pentium p 00007F00 72 6F 63 65 73 73 6F 72 27 73 20 64 75 61 6C 20 70 69 70 65 20 69 73 20 6F 76 65 72 6B 69 6C 6C rocessor's dual pipe is overkill 00007F20 20 66 6F 72 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 20 62 75 74 20 for the Intel486 processor but 00007F40 68 61 73 20 6F 74 68 65 72 77 69 73 65 20 6C 69 74 74 6C 65 20 65 66 66 65 63 74 20 6F 6E 20 69 has otherwise little effect on i 00007F60 74 73 20 70 65 72 66 6F 72 6D 61 6E 63 65 2E 0D 0A 0D 0A 54 68 65 20 66 6F 6C 6C 6F 77 69 6E 67 ts performance.♪◙♪◙The following 00007F80 20 73 75 62 73 65 63 74 69 6F 6E 73 20 61 72 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 subsections are Pentium process 00007FA0 6F 72 20 73 70 65 63 69 66 69 63 20 6F 70 74 69 6D 69 7A 61 74 69 6F 6E 73 2E 20 54 68 65 73 65 or specific optimizations. These 00007FC0 20 6F 70 74 69 6D 69 7A 61 74 69 6F 6E 73 20 64 6F 20 6E 6F 74 20 61 64 76 65 72 73 65 6C 79 20 optimizations do not adversely 00007FE0 69 6D 70 61 63 74 20 74 68 65 20 49 6E 74 65 6C 33 38 36 20 61 6E 64 20 49 6E 74 65 6C 34 38 36 impact the Intel386 and Intel486 00008000 20 70 72 6F 63 65 73 73 6F 72 73 2E 0D 0A 0D 0A 35 2E 36 2E 31 2E 20 50 61 69 72 69 6E 67 0D 0A processors.♪◙♪◙5.6.1. Pairing♪◙ 00008020 0D 0A 50 61 69 72 69 6E 67 20 63 61 6E 6E 6F 74 20 62 65 20 70 65 72 66 6F 72 6D 65 64 20 77 68 ♪◙Pairing cannot be performed wh 00008040 65 6E 20 74 68 65 20 66 6F 6C 6C 6F 77 69 6E 67 20 63 6F 6E 64 69 74 69 6F 6E 73 20 6F 63 63 75 en the following conditions occu 00008060 72 3A 0D 0A 0D 0A 31 2E 20 54 68 65 20 6E 65 78 74 20 74 77 6F 20 69 6E 73 74 72 75 63 74 69 6F r:♪◙♪◙1. The next two instructio 00008080 6E 73 20 61 72 65 20 6E 6F 74 20 70 61 69 72 61 62 6C 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 ns are not pairable instructions 000080A0 20 28 53 65 65 20 41 70 70 65 6E 64 69 78 20 41 20 66 6F 72 20 70 61 69 72 69 6E 67 20 63 68 61 (See Appendix A for pairing cha 000080C0 72 61 63 74 65 72 69 73 74 69 63 73 20 6F 66 20 69 6E 64 69 76 69 64 75 61 6C 20 69 6E 73 74 72 racteristics of individual instr 000080E0 75 63 74 69 6F 6E 73 2E 20 20 49 6E 20 67 65 6E 65 72 61 6C 2C 20 6D 6F 73 74 20 73 69 6D 70 6C uctions. In general, most simpl 00008100 65 20 41 4C 55 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 61 72 65 20 70 61 69 72 61 62 6C 65 2E e ALU instructions are pairable. 00008120 0D 0A 0D 0A 32 2E 20 54 68 65 20 6E 65 78 74 20 74 77 6F 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 ♪◙♪◙2. The next two instructions 00008140 20 68 61 76 65 20 73 6F 6D 65 20 74 79 70 65 20 6F 66 20 72 65 67 69 73 74 65 72 20 63 6F 6E 74 have some type of register cont 00008160 65 6E 74 69 6F 6E 20 28 69 6D 70 6C 69 63 69 74 20 6F 72 20 65 78 70 6C 69 63 69 74 29 2E 20 54 ention (implicit or explicit). T 00008180 68 65 72 65 20 61 72 65 20 73 6F 6D 65 20 73 70 65 63 69 61 6C 20 65 78 63 65 70 74 69 6F 6E 73 here are some special exceptions 000081A0 20 74 6F 20 74 68 69 73 20 72 75 6C 65 20 77 68 65 72 65 20 72 65 67 69 73 74 65 72 20 63 6F 6E to this rule where register con 000081C0 74 65 6E 74 69 6F 6E 20 63 61 6E 20 6F 63 63 75 72 20 77 69 74 68 20 70 61 69 72 69 6E 67 2E 20 tention can occur with pairing. 000081E0 54 68 65 73 65 20 61 72 65 20 64 65 73 63 72 69 62 65 64 20 6C 61 74 65 72 2E 0D 0A 0D 0A 33 2E These are described later.♪◙♪◙3. 00008200 20 54 68 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 61 72 65 20 6E 6F 74 20 62 6F 74 68 20 69 The instructions are not both i 00008220 6E 20 74 68 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 63 61 63 68 65 2E 20 20 41 6E 20 65 78 63 n the instruction cache. An exc 00008240 65 70 74 69 6F 6E 20 74 6F 20 74 68 69 73 20 77 68 69 63 68 20 70 65 72 6D 69 74 73 20 70 61 69 eption to this which permits pai 00008260 72 69 6E 67 20 69 73 20 69 66 20 74 68 65 20 66 69 72 73 74 20 69 6E 73 74 72 75 63 74 69 6F 6E ring is if the first instruction 00008280 20 69 73 20 61 20 6F 6E 65 20 62 79 74 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 2E 0D 0A 0D 0A 35 is a one byte instruction.♪◙♪◙5 000082A0 2E 36 2E 32 2E 20 20 49 6E 73 74 72 75 63 74 69 6F 6E 20 53 65 74 20 50 61 69 72 61 62 69 6C 69 .6.2. Instruction Set Pairabili 000082C0 74 79 0D 0A 0D 0A 35 2E 36 2E 32 2E 31 20 20 55 6E 70 61 69 72 61 62 6C 65 20 69 6E 73 74 72 75 ty♪◙♪◙5.6.2.1 Unpairable instru 000082E0 63 74 69 6F 6E 73 20 28 4E 50 29 0D 0A 0D 0A 31 2E 20 73 68 69 66 74 2F 72 6F 74 61 74 65 20 77 ctions (NP)♪◙♪◙1. shift/rotate w 00008300 69 74 68 20 74 68 65 20 73 68 69 66 74 20 63 6F 75 6E 74 20 69 6E 20 63 6C 0D 0A 0D 0A 32 2E 20 ith the shift count in cl♪◙♪◙2. 00008320 4C 6F 6E 67 2D 41 72 69 74 68 6D 65 74 69 63 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 2C 20 66 6F Long-Arithmetic instructions, fo 00008340 72 20 65 78 61 6D 70 6C 65 2C 20 20 6D 75 6C 2C 20 64 69 76 0D 0A 0D 0A 33 2E 20 45 78 74 65 6E r example, mul, div♪◙♪◙3. Exten 00008360 64 65 64 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 2C 20 66 6F 72 20 65 78 61 6D 70 6C 65 2C 20 72 ded instructions, for example, r 00008380 65 74 2C 20 65 6E 74 65 72 2C 20 70 75 73 68 61 2C 20 6D 6F 76 73 2C 20 72 65 70 20 73 74 6F 73 et, enter, pusha, movs, rep stos 000083A0 2C 20 6C 6F 6F 70 6E 7A 0D 0A 0D 0A 34 2E 20 53 6F 6D 65 20 46 6C 6F 61 74 69 6E 67 2D 50 6F 69 , loopnz♪◙♪◙4. Some Floating-Poi 000083C0 6E 74 20 49 6E 73 74 72 75 63 74 69 6F 6E 73 2C 20 66 6F 72 20 65 78 61 6D 70 6C 65 2C 20 66 73 nt Instructions, for example, fs 000083E0 63 61 6C 65 2C 20 66 6C 64 63 77 2C 20 66 73 74 0D 0A 0D 0A 35 2E 20 49 6E 74 65 72 2D 73 65 67 cale, fldcw, fst♪◙♪◙5. Inter-seg 00008400 6D 65 6E 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 2C 20 66 6F 72 20 65 78 61 6D 70 6C 65 2C 20 ment instructions, for example, 00008420 70 75 73 68 20 73 72 65 67 2C 20 63 61 6C 6C 20 66 61 72 0D 0A 0D 0A 35 2E 36 2E 32 2E 32 20 20 push sreg, call far♪◙♪◙5.6.2.2 00008440 20 50 61 69 72 61 62 6C 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 69 73 73 75 65 64 20 74 6F Pairable instructions issued to 00008460 20 55 20 6F 72 20 56 20 20 70 69 70 65 73 20 28 55 56 29 0D 0A 0D 0A 31 2E 20 4D 6F 73 74 20 38 U or V pipes (UV)♪◙♪◙1. Most 8 00008480 2F 33 32 2D 62 69 74 20 41 4C 55 20 6F 70 65 72 61 74 69 6F 6E 73 2C 20 66 6F 72 20 65 78 61 6D /32-bit ALU operations, for exam 000084A0 70 6C 65 2C 20 61 64 64 2C 20 69 6E 63 2C 20 78 6F 72 2C 0D 0A 0D 0A 32 2E 20 41 6C 6C 20 38 2F ple, add, inc, xor,♪◙♪◙2. All 8/ 000084C0 33 32 2D 62 69 74 20 63 6F 6D 70 61 72 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 2C 20 66 6F 72 32-bit compare instructions, for 000084E0 20 65 78 61 6D 70 6C 65 20 63 6D 70 2C 20 74 65 73 74 0D 0A 0D 0A 33 2E 20 41 6C 6C 20 38 2F 33 example cmp, test♪◙♪◙3. All 8/3 00008500 32 2D 62 69 74 20 73 74 61 63 6B 20 6F 70 65 72 61 74 69 6F 6E 73 20 75 73 69 6E 67 20 72 65 67 2-bit stack operations using reg 00008520 69 73 74 65 72 73 2C 20 66 6F 72 20 65 78 61 6D 70 6C 65 2C 20 70 75 73 68 20 72 65 67 2C 20 70 isters, for example, push reg, p 00008540 6F 70 20 72 65 67 0D 0A 0D 0A 20 35 2E 36 2E 32 2E 33 20 20 50 61 69 72 61 62 6C 65 20 69 6E 73 op reg♪◙♪◙ 5.6.2.3 Pairable ins 00008560 74 72 75 63 74 69 6F 6E 73 20 69 73 73 75 65 64 20 74 6F 20 55 20 70 69 70 65 20 28 50 55 29 0D tructions issued to U pipe (PU)♪ 00008580 0A 0D 0A 54 68 65 73 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 6D 75 73 74 20 62 65 20 69 73 ◙♪◙These instructions must be is 000085A0 73 75 65 64 20 74 6F 20 74 68 65 20 55 20 70 69 70 65 20 61 6E 64 20 63 61 6E 20 70 61 69 72 20 sued to the U pipe and can pair 000085C0 77 69 74 68 20 61 20 73 75 69 74 61 62 6C 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 69 6E 20 74 with a suitable instruction in t 000085E0 68 65 20 56 0D 0A 50 69 70 65 2E 20 54 68 65 73 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 6E he V♪◙Pipe. These instructions n 00008600 65 76 65 72 20 65 78 65 63 75 74 65 20 69 6E 20 74 68 65 20 56 20 70 69 70 65 2E 0D 0A 0D 0A 31 ever execute in the V pipe.♪◙♪◙1 00008620 2E 20 43 61 72 72 79 20 61 6E 64 20 62 6F 72 72 6F 77 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 2C . Carry and borrow instructions, 00008640 20 66 6F 72 20 65 78 61 6D 70 6C 65 2C 20 61 64 63 2C 20 73 62 62 0D 0A 0D 0A 32 2E 20 50 72 65 for example, adc, sbb♪◙♪◙2. Pre 00008660 66 69 78 65 64 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 28 73 65 65 20 6E 65 78 74 20 73 65 63 fixed instructions (see next sec 00008680 74 69 6F 6E 29 0D 0A 0D 0A 33 2E 20 53 68 69 66 74 20 77 69 74 68 20 69 6D 6D 65 64 69 61 74 65 tion)♪◙♪◙3. Shift with immediate 000086A0 0D 0A 0D 0A 34 2E 20 53 6F 6D 65 20 46 6C 6F 61 74 69 6E 67 2D 50 6F 69 6E 74 20 4F 70 65 72 61 ♪◙♪◙4. Some Floating-Point Opera 000086C0 74 69 6F 6E 73 2C 20 66 6F 72 20 65 78 61 6D 70 6C 65 2C 20 66 61 64 64 2C 20 66 6D 75 6C 2C 20 tions, for example, fadd, fmul, 000086E0 66 6C 64 0D 0A 0D 0A 35 2E 36 2E 32 2E 34 20 20 50 61 69 72 61 62 6C 65 20 69 6E 73 74 72 75 63 fld♪◙♪◙5.6.2.4 Pairable instruc 00008700 74 69 6F 6E 73 20 69 73 73 75 65 64 20 74 6F 20 56 20 20 70 69 70 65 20 28 50 56 29 0D 0A 0D 0A tions issued to V pipe (PV)♪◙♪◙ 00008720 54 68 65 73 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 63 61 6E 20 65 78 65 63 75 74 65 20 69 These instructions can execute i 00008740 6E 20 65 69 74 68 65 72 20 74 68 65 20 55 20 70 69 70 65 20 6F 72 20 74 68 65 20 56 20 70 69 70 n either the U pipe or the V pip 00008760 65 2C 20 62 75 74 20 74 68 65 79 20 61 72 65 20 6F 6E 6C 79 20 70 61 69 72 65 64 20 77 68 65 6E e, but they are only paired when 00008780 20 74 68 65 79 20 61 72 65 20 69 6E 20 74 68 65 20 56 20 20 70 69 70 65 2E 20 53 69 6E 63 65 20 they are in the V pipe. Since 000087A0 74 68 65 73 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 63 68 61 6E 67 65 20 74 68 65 20 69 6E these instructions change the in 000087C0 73 74 72 75 63 74 69 6F 6E 20 70 6F 69 6E 74 65 72 20 28 65 69 70 29 2C 20 74 68 65 79 20 63 61 struction pointer (eip), they ca 000087E0 6E 6E 6F 74 20 70 61 69 72 20 69 6E 20 74 68 65 20 55 20 70 69 70 65 20 62 65 63 61 75 73 65 20 nnot pair in the U pipe because 00008800 74 68 65 20 6E 65 78 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 6D 61 79 20 6E 6F 74 20 62 65 20 the next instruction may not be 00008820 61 64 6A 61 63 65 6E 74 2E 20 45 76 65 6E 20 77 68 65 6E 20 61 20 62 72 61 6E 63 68 20 69 6E 20 adjacent. Even when a branch in 00008840 74 68 65 20 55 20 70 69 70 65 20 69 73 20 70 72 65 64 69 63 74 65 64 20 22 6E 6F 74 20 74 61 6B the U pipe is predicted "not tak 00008860 65 6E 22 2C 20 69 74 20 77 69 6C 6C 20 6E 6F 74 20 70 61 69 72 20 77 69 74 68 20 74 68 65 20 66 en", it will not pair with the f 00008880 6F 6C 6C 6F 77 69 6E 67 20 69 6E 73 74 72 75 63 74 69 6F 6E 2E 0D 0A 0D 0A 31 2E 20 53 69 6D 70 ollowing instruction.♪◙♪◙1. Simp 000088A0 6C 65 20 63 6F 6E 74 72 6F 6C 20 74 72 61 6E 73 66 65 72 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 le control transfer instructions 000088C0 2C 20 66 6F 72 20 65 78 61 6D 70 6C 65 20 2D 20 63 61 6C 6C 20 6E 65 61 72 2C 20 6A 6D 70 20 6E , for example - call near, jmp n 000088E0 65 61 72 2C 20 6A 63 63 2E 20 54 68 69 73 20 69 6E 63 6C 75 64 65 73 20 62 6F 74 68 20 74 68 65 ear, jcc. This includes both the 00008900 20 6A 63 63 20 73 68 6F 72 74 20 61 6E 64 20 74 68 65 20 6A 63 63 20 6E 65 61 72 20 28 77 68 69 jcc short and the jcc near (whi 00008920 63 68 20 68 61 73 20 61 20 30 66 20 70 72 65 66 69 78 29 20 76 65 72 73 69 6F 6E 73 20 6F 66 20 ch has a 0f prefix) versions of 00008940 74 68 65 20 63 6F 6E 64 69 74 69 6F 6E 61 6C 20 6A 75 6D 70 20 69 6E 73 74 72 75 63 74 69 6F 6E the conditional jump instruction 00008960 73 2E 0D 0A 0D 0A 32 2E 20 66 78 63 68 0D 0A 0D 0A 35 2E 36 2E 33 2E 20 20 55 6E 70 61 69 72 61 s.♪◙♪◙2. fxch♪◙♪◙5.6.3. Unpaira 00008980 62 69 6C 69 74 79 20 44 75 65 20 74 6F 20 52 65 67 69 73 74 65 72 73 0D 0A 0D 0A 54 68 65 20 70 bility Due to Registers♪◙♪◙The p 000089A0 61 69 72 61 62 69 6C 69 74 79 20 6F 66 20 61 6E 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 69 73 20 airability of an instruction is 000089C0 61 6C 73 6F 20 61 66 66 65 63 74 65 64 20 62 79 20 69 74 73 20 6F 70 65 72 61 6E 64 73 2E 20 54 also affected by its operands. T 000089E0 68 65 20 66 6F 6C 6C 6F 77 69 6E 67 20 61 72 65 20 74 68 65 20 63 6F 6D 62 69 6E 61 74 69 6F 6E he following are the combination 00008A00 73 20 74 68 61 74 20 61 72 65 20 6E 6F 74 20 70 61 69 72 61 62 6C 65 20 64 75 65 20 74 6F 20 72 s that are not pairable due to r 00008A20 65 67 69 73 74 65 72 20 63 6F 6E 74 65 6E 74 69 6F 6E 2E 20 45 78 63 65 70 74 69 6F 6E 73 20 74 egister contention. Exceptions t 00008A40 6F 20 74 68 65 73 65 20 72 75 6C 65 73 20 61 72 65 20 67 69 76 65 6E 20 69 6E 20 74 68 65 20 6E o these rules are given in the n 00008A60 65 78 74 20 73 65 63 74 69 6F 6E 2E 0D 0A 0D 0A 31 2E 20 54 68 65 20 66 69 72 73 74 20 69 6E 73 ext section.♪◙♪◙1. The first ins 00008A80 74 72 75 63 74 69 6F 6E 20 77 72 69 74 65 73 20 74 6F 20 61 20 72 65 67 69 73 74 65 72 20 74 68 truction writes to a register th 00008AA0 61 74 20 74 68 65 20 73 65 63 6F 6E 64 20 6F 6E 65 20 72 65 61 64 73 20 66 72 6F 6D 20 28 66 6C at the second one reads from (fl 00008AC0 6F 77 2D 64 65 70 65 6E 64 65 6E 63 65 29 2E 0D 0A 0D 0A 45 78 61 6D 70 6C 65 3A 0D 0A 0D 0A 20 ow-dependence).♪◙♪◙Example:♪◙♪◙ 00008AE0 20 20 20 20 6D 6F 76 20 20 65 61 78 2C 20 38 0D 0A 20 20 20 20 20 6D 6F 76 20 20 5B 65 62 70 5D mov eax, 8♪◙ mov [ebp] 00008B00 2C 20 65 61 78 0D 0A 0D 0A 0C 32 2E 20 42 6F 74 68 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 77 , eax♪◙♪◙♀2. Both instructions w 00008B20 72 69 74 65 20 74 6F 20 74 68 65 20 73 61 6D 65 20 72 65 67 69 73 74 65 72 20 28 6F 75 74 70 75 rite to the same register (outpu 00008B40 74 2D 64 65 70 65 6E 64 65 6E 63 65 29 2E 0D 0A 0D 0A 45 78 61 6D 70 6C 65 3A 0D 0A 0D 0A 20 20 t-dependence).♪◙♪◙Example:♪◙♪◙ 00008B60 20 20 20 6D 6F 76 20 20 65 61 78 2C 20 38 0D 0A 20 20 20 20 20 6D 6F 76 20 20 65 61 78 2C 20 5B mov eax, 8♪◙ mov eax, [ 00008B80 65 62 70 5D 0D 0A 0D 0A 54 68 69 73 20 6C 69 6D 69 74 61 74 69 6F 6E 20 64 6F 65 73 20 6E 6F 74 ebp]♪◙♪◙This limitation does not 00008BA0 20 61 70 70 6C 79 20 74 6F 20 61 20 70 61 69 72 20 6F 66 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 apply to a pair of instructions 00008BC0 20 77 68 69 63 68 20 77 72 69 74 65 20 74 6F 20 74 68 65 20 65 66 6C 61 67 73 20 72 65 67 69 73 which write to the eflags regis 00008BE0 74 65 72 20 28 65 2E 67 2E 20 74 77 6F 20 41 4C 55 20 6F 70 65 72 61 74 69 6F 6E 73 20 74 68 61 ter (e.g. two ALU operations tha 00008C00 74 20 63 68 61 6E 67 65 20 74 68 65 20 63 6F 6E 64 69 74 69 6F 6E 20 63 6F 64 65 73 29 2E 20 54 t change the condition codes). T 00008C20 68 65 20 63 6F 6E 64 69 74 69 6F 6E 20 63 6F 64 65 20 61 66 74 65 72 20 74 68 65 20 70 61 69 72 he condition code after the pair 00008C40 65 64 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 65 78 65 63 75 74 65 20 77 69 6C 6C 20 68 61 76 ed instructions execute will hav 00008C60 65 20 74 68 65 20 63 6F 6E 64 69 74 69 6F 6E 20 66 72 6F 6D 20 74 68 65 20 56 20 70 69 70 65 20 e the condition from the V pipe 00008C80 69 6E 73 74 72 75 63 74 69 6F 6E 2E 0D 0A 0D 0A 4E 6F 74 65 20 74 68 61 74 20 61 20 70 61 69 72 instruction.♪◙♪◙Note that a pair 00008CA0 20 6F 66 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 69 6E 20 77 68 69 63 68 20 74 68 65 20 66 69 of instructions in which the fi 00008CC0 72 73 74 20 72 65 61 64 73 20 61 20 72 65 67 69 73 74 65 72 20 61 6E 64 20 74 68 65 20 73 65 63 rst reads a register and the sec 00008CE0 6F 6E 64 20 77 72 69 74 65 73 20 74 6F 20 69 74 20 28 61 6E 74 69 2D 20 64 65 70 65 6E 64 65 6E ond writes to it (anti- dependen 00008D00 63 65 29 20 69 73 20 70 61 69 72 61 62 6C 65 2E 0D 0A 0D 0A 45 78 61 6D 70 6C 65 3A 0D 0A 0D 0A ce) is pairable.♪◙♪◙Example:♪◙♪◙ 00008D20 20 20 20 20 20 6D 6F 76 20 20 65 61 78 2C 20 65 62 78 20 20 20 20 20 20 20 6D 6F 76 20 20 65 62 mov eax, ebx mov eb 00008D40 78 2C 20 5B 65 62 70 5D 0D 0A 0D 0A 46 6F 72 20 70 75 72 70 6F 73 65 73 20 6F 66 20 64 65 74 65 x, [ebp]♪◙♪◙For purposes of dete 00008D60 72 6D 69 6E 69 6E 67 20 72 65 67 69 73 74 65 72 20 63 6F 6E 74 65 6E 74 69 6F 6E 2C 20 61 20 72 rmining register contention, a r 00008D80 65 66 65 72 65 6E 63 65 20 74 6F 20 61 20 62 79 74 65 20 6F 72 20 77 6F 72 64 20 72 65 67 69 73 eference to a byte or word regis 00008DA0 74 65 72 20 69 73 20 74 72 65 61 74 65 64 0D 0A 61 73 20 61 20 72 65 66 65 72 65 6E 63 65 20 74 ter is treated♪◙as a reference t 00008DC0 6F 20 74 68 65 20 63 6F 6E 74 61 69 6E 69 6E 67 20 33 32 2D 62 69 74 20 72 65 67 69 73 74 65 72 o the containing 32-bit register 00008DE0 2E 20 48 65 6E 63 65 2C 0D 0A 0D 0A 20 20 20 20 20 6D 6F 76 20 20 61 6C 2C 20 31 0D 0A 20 20 20 . Hence,♪◙♪◙ mov al, 1♪◙ 00008E00 20 20 6D 6F 76 20 20 61 68 2C 20 30 0D 0A 0D 0A 64 6F 20 6E 6F 74 20 70 61 69 72 20 64 75 65 20 mov ah, 0♪◙♪◙do not pair due 00008E20 74 6F 20 61 70 70 61 72 65 6E 74 20 6F 75 74 70 75 74 20 64 65 70 65 6E 64 65 6E 63 69 65 73 20 to apparent output dependencies 00008E40 6F 6E 20 65 61 78 2E 0D 0A 0D 0A 35 2E 36 2E 34 20 53 70 65 63 69 61 6C 20 50 61 69 72 73 0D 0A on eax.♪◙♪◙5.6.4 Special Pairs♪◙ 00008E60 0D 0A 54 68 65 72 65 20 61 72 65 20 73 6F 6D 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 74 68 ♪◙There are some instructions th 00008E80 61 74 20 63 61 6E 20 62 65 20 70 61 69 72 65 64 20 61 6C 74 68 6F 75 67 68 20 74 68 65 20 67 65 at can be paired although the ge 00008EA0 6E 65 72 61 6C 20 72 75 6C 65 20 70 72 6F 68 69 62 69 74 73 20 74 68 69 73 2E 20 54 68 65 73 65 neral rule prohibits this. These 00008EC0 20 73 70 65 63 69 61 6C 20 70 61 69 72 73 20 6F 76 65 72 63 6F 6D 65 20 72 65 67 69 73 74 65 72 special pairs overcome register 00008EE0 20 64 65 70 65 6E 64 65 6E 63 69 65 73 2E 20 4D 6F 73 74 20 6F 66 20 74 68 65 73 65 20 65 78 63 dependencies. Most of these exc 00008F00 65 70 74 69 6F 6E 73 20 69 6E 76 6F 6C 76 65 20 69 6D 70 6C 69 63 69 74 20 72 65 61 64 73 2F 77 eptions involve implicit reads/w 00008F20 72 69 74 65 73 20 74 6F 20 74 68 65 20 65 73 70 20 72 65 67 69 73 74 65 72 20 6F 72 20 69 6D 70 rites to the esp register or imp 00008F40 6C 69 63 69 74 20 77 72 69 74 65 73 20 74 6F 20 74 68 65 20 63 6F 6E 64 69 74 69 6F 6E 20 63 6F licit writes to the condition co 00008F60 64 65 73 3A 0D 0A 0D 0A 53 74 61 63 6B 20 50 6F 69 6E 74 65 72 3A 0D 0A 0D 0A 31 2E 20 70 75 73 des:♪◙♪◙Stack Pointer:♪◙♪◙1. pus 00008F80 68 20 72 65 67 2F 69 6D 6D 3B 20 70 75 73 68 20 72 65 67 2F 69 6D 6D 0D 0A 0D 0A 32 2E 20 70 75 h reg/imm; push reg/imm♪◙♪◙2. pu 00008FA0 73 68 20 72 65 67 2F 69 6D 6D 3B 20 63 61 6C 6C 0D 0A 0D 0A 33 2E 20 70 6F 70 20 72 65 67 20 20 sh reg/imm; call♪◙♪◙3. pop reg 00008FC0 20 20 20 3B 20 70 6F 70 20 72 65 67 0D 0A 0D 0A 43 6F 6E 64 69 74 69 6F 6E 20 43 6F 64 65 73 3A ; pop reg♪◙♪◙Condition Codes: 00008FE0 0D 0A 0D 0A 31 2E 20 63 6D 70 20 20 20 20 20 20 20 20 20 3B 20 6A 63 63 0D 0A 0D 0A 32 2E 20 61 ♪◙♪◙1. cmp ; jcc♪◙♪◙2. a 00009000 64 64 20 20 20 20 20 20 20 20 20 3B 20 6A 6E 65 0D 0A 0D 0A 4E 6F 74 65 20 74 68 61 74 20 74 68 dd ; jne♪◙♪◙Note that th 00009020 65 20 73 70 65 63 69 61 6C 20 70 61 69 72 73 20 74 68 61 74 20 63 6F 6E 73 69 73 74 20 6F 66 20 e special pairs that consist of 00009040 70 75 73 68 2F 70 6F 70 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 6D 61 79 20 68 61 76 65 20 6F push/pop instructions may have o 00009060 6E 6C 79 20 69 6D 6D 65 64 69 61 74 65 20 6F 72 20 72 65 67 69 73 74 65 72 20 6F 70 65 72 61 6E nly immediate or register operan 00009080 64 73 2E 0D 0A 0D 0A 0C 35 2E 36 2E 35 20 52 65 73 74 72 69 63 74 69 6F 6E 73 20 6F 6E 20 50 61 ds.♪◙♪◙♀5.6.5 Restrictions on Pa 000090A0 69 72 20 45 78 65 63 75 74 69 6F 6E 0D 0A 0D 0A 54 68 65 72 65 20 61 72 65 20 73 6F 6D 65 20 70 ir Execution♪◙♪◙There are some p 000090C0 61 69 72 73 20 74 68 61 74 20 6D 61 79 20 62 65 20 69 73 73 75 65 64 20 73 69 6D 75 6C 74 61 6E airs that may be issued simultan 000090E0 65 6F 75 73 6C 79 20 62 75 74 20 77 69 6C 6C 20 6E 6F 74 20 65 78 65 63 75 74 65 20 69 6E 20 70 eously but will not execute in p 00009100 61 72 61 6C 6C 65 6C 3A 0D 0A 0D 0A 31 2E 20 49 66 20 62 6F 74 68 20 69 6E 73 74 72 75 63 74 69 arallel:♪◙♪◙1. If both instructi 00009120 6F 6E 73 20 61 63 63 65 73 73 20 74 68 65 20 73 61 6D 65 20 64 61 74 61 2D 63 61 63 68 65 20 6D ons access the same data-cache m 00009140 65 6D 6F 72 79 20 62 61 6E 6B 20 74 68 65 6E 20 74 68 65 20 73 65 63 6F 6E 64 20 72 65 71 75 65 emory bank then the second reque 00009160 73 74 20 28 56 20 20 70 69 70 65 29 20 6D 75 73 74 20 77 61 69 74 20 66 6F 72 20 74 68 65 20 66 st (V pipe) must wait for the f 00009180 69 72 73 74 20 72 65 71 75 65 73 74 20 74 6F 20 63 6F 6D 70 6C 65 74 65 2E 20 41 20 62 61 6E 6B irst request to complete. A bank 000091A0 20 63 6F 6E 66 6C 69 63 74 20 6F 63 63 75 72 73 20 77 68 65 6E 20 62 69 74 73 20 32 2D 34 20 61 conflict occurs when bits 2-4 a 000091C0 72 65 20 74 68 65 20 73 61 6D 65 20 69 6E 20 74 68 65 20 74 77 6F 20 70 68 79 73 69 63 61 6C 20 re the same in the two physical 000091E0 61 64 64 72 65 73 73 65 73 2E 20 54 68 69 73 20 69 73 20 62 65 63 61 75 73 65 20 74 68 65 20 63 addresses. This is because the c 00009200 61 63 68 65 20 69 73 20 6F 72 67 61 6E 69 7A 65 64 20 61 73 20 38 20 62 61 6E 6B 73 20 6F 66 20 ache is organized as 8 banks of 00009220 33 32 2D 62 69 74 20 77 69 64 65 20 64 61 74 61 20 65 6E 74 72 69 65 73 2E 20 41 20 62 61 6E 6B 32-bit wide data entries. A bank 00009240 20 63 6F 6E 66 6C 69 63 74 20 69 6E 63 75 72 73 20 61 20 6F 6E 65 20 63 6C 6F 63 6B 20 70 65 6E conflict incurs a one clock pen 00009260 61 6C 74 79 20 6F 6E 20 74 68 65 20 56 20 70 69 70 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 2E alty on the V pipe instruction . 00009280 0D 0A 0D 0A 32 2E 20 49 6E 74 65 72 2D 70 69 70 65 20 63 6F 6E 63 75 72 72 65 6E 63 79 20 69 6E ♪◙♪◙2. Inter-pipe concurrency in 000092A0 20 65 78 65 63 75 74 69 6F 6E 20 70 72 65 73 65 72 76 65 73 20 6D 65 6D 6F 72 79 2D 61 63 63 65 execution preserves memory-acce 000092C0 73 73 20 6F 72 64 65 72 69 6E 67 2E 20 41 20 6D 75 6C 74 69 2D 63 79 63 6C 65 20 69 6E 73 74 72 ss ordering. A multi-cycle instr 000092E0 75 63 74 69 6F 6E 20 69 6E 20 74 68 65 20 55 20 70 69 70 65 20 77 69 6C 6C 20 65 78 65 63 75 74 uction in the U pipe will execut 00009300 65 20 61 6C 6F 6E 65 20 75 6E 74 69 6C 20 69 74 73 20 6C 61 73 74 20 6D 65 6D 6F 72 79 20 61 63 e alone until its last memory ac 00009320 63 65 73 73 2E 0D 0A 0D 0A 09 61 64 64 20 20 65 61 78 2C 20 6D 65 6D 6C 09 61 64 64 20 20 65 62 cess.♪◙♪◙○add eax, meml○add eb 00009340 78 2C 20 6D 65 6D 32 20 09 3B 20 31 0D 0A 09 20 20 28 61 64 64 29 09 20 20 20 28 61 64 64 29 09 x, mem2 ○; 1♪◙○ (add)○ (add)○ 00009360 3B 20 32 20 20 32 2D 63 79 63 6C 65 0D 0A 0D 0A 54 68 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 ; 2 2-cycle♪◙♪◙The instructions 00009380 20 61 62 6F 76 65 20 61 64 64 20 74 68 65 20 63 6F 6E 74 65 6E 74 73 20 6F 66 20 74 68 65 20 72 above add the contents of the r 000093A0 65 67 69 73 74 65 72 20 61 6E 64 20 74 68 65 20 76 61 6C 75 65 20 61 74 20 74 68 65 20 6D 65 6D egister and the value at the mem 000093C0 6F 72 79 20 6C 6F 63 61 74 69 6F 6E 2C 20 74 68 65 6E 20 70 75 74 20 74 68 65 20 72 65 73 75 6C ory location, then put the resul 000093E0 74 20 69 6E 20 74 68 65 20 72 65 67 69 73 74 65 72 2E 20 41 6E 20 61 64 64 20 77 69 74 68 20 61 t in the register. An add with a 00009400 20 6D 65 6D 6F 72 79 20 6F 70 65 72 61 6E 64 20 74 61 6B 65 73 20 74 77 6F 20 63 6C 6F 63 6B 73 memory operand takes two clocks 00009420 20 74 6F 20 65 78 65 63 75 74 65 2E 20 54 68 65 20 66 69 72 73 74 20 63 6C 6F 63 6B 20 6C 6F 61 to execute. The first clock loa 00009440 64 73 20 74 68 65 20 76 61 6C 75 65 20 66 72 6F 6D 20 63 61 63 68 65 2C 20 61 6E 64 20 74 68 65 ds the value from cache, and the 00009460 20 73 65 63 6F 6E 64 20 63 6C 6F 63 6B 20 70 65 72 66 6F 72 6D 73 20 74 68 65 20 61 64 64 69 74 second clock performs the addit 00009480 69 6F 6E 2E 20 53 69 6E 63 65 20 74 68 65 72 65 20 69 73 20 6F 6E 6C 79 20 6F 6E 65 20 6D 65 6D ion. Since there is only one mem 000094A0 6F 72 79 20 61 63 63 65 73 73 20 69 6E 20 74 68 65 20 55 20 70 69 70 65 20 69 6E 73 74 72 75 63 ory access in the U pipe instruc 000094C0 74 69 6F 6E 2C 20 74 68 65 20 61 64 64 20 69 6E 20 74 68 65 20 56 20 20 70 69 70 65 20 63 61 6E tion, the add in the V pipe can 000094E0 20 73 74 61 72 74 20 69 6E 20 74 68 65 20 73 61 6D 65 20 63 79 63 6C 65 2E 0D 0A 0D 0A 09 61 64 start in the same cycle.♪◙♪◙○ad 00009500 64 20 20 6D 65 6D 6C 2C 20 65 61 78 09 09 20 3B 20 31 0D 0A 20 09 20 20 20 28 61 64 64 29 20 09 d meml, eax○○ ; 1♪◙ ○ (add) ○ 00009520 09 3B 20 32 0D 0A 20 20 09 20 20 20 28 61 64 64 29 09 61 64 64 20 20 6D 65 6D 32 2C 20 65 62 78 ○; 2♪◙ ○ (add)○add mem2, ebx 00009540 09 3B 20 33 0D 0A 09 09 20 20 20 28 61 64 64 29 09 3B 20 34 0D 0A 09 09 20 20 20 28 61 64 64 29 ○; 3♪◙○○ (add)○; 4♪◙○○ (add) 00009560 09 3B 20 35 0D 0A 0D 0A 54 68 65 20 61 62 6F 76 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 61 ○; 5♪◙♪◙The above instructions a 00009580 64 64 20 74 68 65 20 63 6F 6E 74 65 6E 74 73 20 6F 66 20 74 68 65 20 72 65 67 69 73 74 65 72 20 dd the contents of the register 000095A0 74 6F 20 74 68 65 20 6D 65 6D 6F 72 79 20 6C 6F 63 61 74 69 6F 6E 20 61 6E 64 20 73 74 6F 72 65 to the memory location and store 000095C0 20 74 68 65 20 72 65 73 75 6C 74 20 61 74 20 74 68 65 20 6D 65 6D 6F 72 79 20 6C 6F 63 61 74 69 the result at the memory locati 000095E0 6F 6E 2E 20 41 6E 20 61 64 64 20 77 69 74 68 20 61 20 6D 65 6D 6F 72 79 20 72 65 73 75 6C 74 20 on. An add with a memory result 00009600 74 61 6B 65 73 20 33 20 63 6C 6F 63 6B 73 20 74 6F 20 65 78 65 63 75 74 65 2E 20 20 54 68 65 20 takes 3 clocks to execute. The 00009620 66 69 72 73 74 20 63 6C 6F 63 6B 20 6C 6F 61 64 73 20 74 68 65 20 76 61 6C 75 65 2C 20 74 68 65 first clock loads the value, the 00009640 20 73 65 63 6F 6E 64 20 70 65 72 66 6F 72 6D 73 20 74 68 65 20 61 64 64 69 74 69 6F 6E 2C 20 61 second performs the addition, a 00009660 6E 64 20 74 68 65 20 74 68 69 72 64 20 73 74 6F 72 65 73 20 74 68 65 20 72 65 73 75 6C 74 2E 20 nd the third stores the result. 00009680 57 68 65 6E 20 70 61 69 72 65 64 2C 20 74 68 65 20 6C 61 73 74 20 63 79 63 6C 65 20 6F 66 20 74 When paired, the last cycle of t 000096A0 68 65 20 55 20 70 69 70 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 6F 76 65 72 6C 61 70 73 20 77 he U pipe instruction overlaps w 000096C0 69 74 68 20 74 68 65 20 66 69 72 73 74 20 63 79 63 6C 65 20 6F 66 20 74 68 65 20 56 20 70 69 70 ith the first cycle of the V pip 000096E0 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 65 78 65 63 75 74 69 6F 6E 2E 0D 0A 0D 0A 4E 6F 20 6F e instruction execution.♪◙♪◙No o 00009700 74 68 65 72 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 6D 61 79 20 62 65 67 69 6E 20 65 78 65 63 ther instructions may begin exec 00009720 75 74 69 6F 6E 20 75 6E 74 69 6C 20 74 68 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 61 6C 72 ution until the instructions alr 00009740 65 61 64 79 20 65 78 65 63 75 74 69 6E 67 20 68 61 76 65 0D 0A 63 6F 6D 70 6C 65 74 65 64 2E 0D eady executing have♪◙completed.♪ 00009760 0A 0D 0A 54 6F 20 65 78 70 6F 73 65 20 74 68 65 20 6F 70 70 6F 72 74 75 6E 69 74 69 65 73 20 66 ◙♪◙To expose the opportunities f 00009780 6F 72 20 73 63 68 65 64 75 6C 69 6E 67 20 61 6E 64 20 70 61 69 72 69 6E 67 2C 20 69 74 20 69 73 or scheduling and pairing, it is 000097A0 20 62 65 74 74 65 72 20 74 6F 20 69 73 73 75 65 20 61 20 73 65 71 75 65 6E 63 65 20 6F 66 20 73 better to issue a sequence of s 000097C0 69 6D 70 6C 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 72 61 74 68 65 72 20 74 68 61 6E 20 61 imple instructions rather than a 000097E0 20 63 6F 6D 70 6C 65 78 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 74 68 61 74 20 74 61 6B 65 73 20 complex instruction that takes 00009800 74 68 65 20 73 61 6D 65 20 6E 75 6D 62 65 72 20 6F 66 20 63 79 63 6C 65 73 2E 20 54 68 65 20 73 the same number of cycles. The s 00009820 69 6D 70 6C 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 73 65 71 75 65 6E 63 65 20 63 61 6E 20 74 imple instruction sequence can t 00009840 61 6B 65 20 61 64 76 61 6E 74 61 67 65 20 6F 66 20 6D 6F 72 65 20 69 73 73 75 65 20 73 6C 6F 74 ake advantage of more issue slot 00009860 73 2E 20 20 43 6F 6D 70 69 6C 65 72 20 77 72 69 74 65 72 73 2F 70 72 6F 67 72 61 6D 6D 65 72 73 s. Compiler writers/programmers 00009880 20 63 61 6E 20 61 6C 73 6F 20 63 68 6F 6F 73 65 20 74 6F 20 72 65 63 6F 6E 73 74 72 75 63 74 20 can also choose to reconstruct 000098A0 74 68 65 20 63 6F 6D 70 6C 65 78 20 66 6F 72 6D 20 69 66 20 74 68 65 20 70 61 69 72 69 6E 67 20 the complex form if the pairing 000098C0 6F 70 70 6F 72 74 75 6E 69 74 79 20 64 6F 65 73 20 6E 6F 74 20 6D 61 74 65 72 69 61 6C 69 7A 65 opportunity does not materialize 000098E0 2E 20 54 68 65 20 6C 6F 61 64 2F 73 74 6F 72 65 20 73 74 79 6C 65 20 63 6F 64 65 20 67 65 6E 65 . The load/store style code gene 00009900 72 61 74 69 6F 6E 20 72 65 71 75 69 72 65 73 20 6D 6F 72 65 20 72 65 67 69 73 74 65 72 73 20 61 ration requires more registers a 00009920 6E 64 20 69 6E 63 72 65 61 73 65 73 20 63 6F 64 65 20 73 69 7A 65 2E 20 54 68 69 73 20 69 6D 70 nd increases code size. This imp 00009940 61 63 74 73 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 20 70 65 72 66 6F 72 6D 61 acts Intel486 processor performa 00009960 6E 63 65 2C 20 61 6C 74 68 6F 75 67 68 20 6F 6E 6C 79 20 61 73 20 61 20 73 65 63 6F 6E 64 20 6F nce, although only as a second o 00009980 72 64 65 72 20 65 66 66 65 63 74 2E 20 54 6F 20 63 6F 6D 70 65 6E 73 61 74 65 20 66 6F 72 20 74 rder effect. To compensate for t 000099A0 68 65 20 65 78 74 72 61 20 72 65 67 69 73 74 65 72 73 20 6E 65 65 64 65 64 2C 20 65 78 74 72 61 he extra registers needed, extra 000099C0 20 65 66 66 6F 72 74 20 73 68 6F 75 6C 64 20 62 65 20 70 75 74 20 69 6E 74 6F 20 74 68 65 20 72 effort should be put into the r 000099E0 65 67 69 73 74 65 72 20 61 6C 6C 6F 63 61 74 6F 72 20 61 6E 64 20 69 6E 73 74 72 75 63 74 69 6F egister allocator and instructio 00009A00 6E 20 73 63 68 65 64 75 6C 65 72 20 73 6F 20 74 68 61 74 20 65 78 74 72 61 20 72 65 67 69 73 74 n scheduler so that extra regist 00009A20 65 72 73 20 61 72 65 20 6F 6E 6C 79 20 75 73 65 64 20 77 68 65 6E 20 70 61 72 61 6C 6C 65 6C 69 ers are only used when paralleli 00009A40 73 6D 20 69 6E 63 72 65 61 73 65 73 2E 0D 0A 0D 0A 35 2E 37 20 49 6E 74 65 67 65 72 20 49 6E 73 sm increases.♪◙♪◙5.7 Integer Ins 00009A60 74 72 75 63 74 69 6F 6E 20 53 65 6C 65 63 74 69 6F 6E 0D 0A 0D 0A 54 68 65 20 66 6F 6C 6C 6F 77 truction Selection♪◙♪◙The follow 00009A80 69 6E 67 20 68 69 67 68 6C 69 67 68 74 73 20 73 6F 6D 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 ing highlights some instruction 00009AA0 73 65 71 75 65 6E 63 65 73 20 74 6F 20 61 76 6F 69 64 20 61 6E 64 20 73 6F 6D 65 20 73 65 71 75 sequences to avoid and some sequ 00009AC0 65 6E 63 65 73 20 74 6F 20 75 73 65 20 77 68 65 6E 20 67 65 6E 65 72 61 74 69 6E 67 20 6F 70 74 ences to use when generating opt 00009AE0 69 6D 61 6C 20 61 73 73 65 6D 62 6C 79 20 63 6F 64 65 2E 0D 0A 0D 0A 54 68 65 20 6C 65 61 20 69 imal assembly code.♪◙♪◙The lea i 00009B00 6E 73 74 72 75 63 74 69 6F 6E 20 63 61 6E 20 62 65 20 61 64 76 61 6E 74 61 67 65 6F 75 73 3A 0D nstruction can be advantageous:♪ 00009B20 0A 0D 0A 61 2E 20 4C 65 61 20 6D 61 79 20 62 65 20 75 73 65 64 20 73 6F 6D 65 74 69 6D 65 73 20 ◙♪◙a. Lea may be used sometimes 00009B40 61 73 20 61 20 74 68 72 65 65 2F 66 6F 75 72 20 6F 70 65 72 61 6E 64 20 61 64 64 69 74 69 6F 6E as a three/four operand addition 00009B60 20 69 6E 73 74 72 75 63 74 69 6F 6E 0B 20 20 20 20 20 20 20 20 20 20 20 20 65 2E 67 2E 2C 20 20 instruction♂ e.g., 00009B80 6C 65 61 20 20 65 63 78 2C 20 5B 65 61 78 2B 65 62 78 2B 34 2B 61 5D 0D 0A 0D 0A 62 2E 20 49 6E lea ecx, [eax+ebx+4+a]♪◙♪◙b. In 00009BA0 20 6D 61 6E 79 20 63 61 73 65 73 20 61 6E 20 6C 65 61 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 6F many cases an lea instruction o 00009BC0 72 20 61 20 73 65 71 75 65 6E 63 65 20 6F 66 20 6C 65 61 2C 20 61 64 64 2C 20 73 75 62 20 61 6E r a sequence of lea, add, sub an 00009BE0 64 20 74 68 65 20 73 68 69 66 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 6D 61 79 20 62 65 20 d the shift instructions may be 00009C00 75 73 65 64 20 74 6F 20 72 65 70 6C 61 63 65 20 63 6F 6E 73 74 61 6E 74 20 6D 75 6C 74 69 70 6C used to replace constant multipl 00009C20 79 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 2E 0D 0A 0D 0A 63 2E 20 54 68 69 73 20 63 61 6E 20 61 y instructions.♪◙♪◙c. This can a 00009C40 6C 73 6F 20 62 65 20 75 73 65 64 20 74 6F 20 61 76 6F 69 64 20 63 6F 70 79 69 6E 67 20 61 20 72 lso be used to avoid copying a r 00009C60 65 67 69 73 74 65 72 20 77 68 65 6E 20 62 6F 74 68 20 6F 70 65 72 61 6E 64 73 20 74 6F 20 61 6E egister when both operands to an 00009C80 20 61 64 64 20 61 72 65 20 73 74 69 6C 6C 20 6E 65 65 64 65 64 20 20 61 66 74 65 72 20 74 68 65 add are still needed after the 00009CA0 20 61 64 64 2C 20 73 69 6E 63 65 20 6C 65 61 20 6E 65 65 64 20 6E 6F 74 20 6F 76 65 72 77 72 69 add, since lea need not overwri 00009CC0 74 65 20 69 74 73 20 6F 70 65 72 61 6E 64 73 2E 0D 0A 0D 0A 54 68 65 20 64 69 73 61 64 76 61 6E te its operands.♪◙♪◙The disadvan 00009CE0 74 61 67 65 20 6F 66 20 74 68 65 20 6C 65 61 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 69 73 20 74 tage of the lea instruction is t 00009D00 68 61 74 20 69 74 20 69 6E 63 72 65 61 73 65 73 20 74 68 65 20 70 6F 73 73 69 62 69 6C 69 74 79 hat it increases the possibility 00009D20 20 6F 66 20 61 6E 20 41 47 49 20 73 74 61 6C 6C 20 77 69 74 68 20 70 72 65 76 69 6F 75 73 20 69 of an AGI stall with previous i 00009D40 6E 73 74 72 75 63 74 69 6F 6E 73 2E 20 4C 65 61 20 69 73 20 75 73 65 66 75 6C 20 66 6F 72 20 73 nstructions. Lea is useful for s 00009D60 68 69 66 74 73 20 6F 66 20 32 2C 34 2C 38 20 62 65 63 61 75 73 65 20 74 68 65 20 73 68 69 66 74 hifts of 2,4,8 because the shift 00009D80 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 74 61 6B 65 20 32 20 63 6C 6F 63 6B 73 20 6F 6E 20 49 instructions take 2 clocks on I 00009DA0 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 20 77 68 65 72 65 61 73 20 6C 65 61 20 6F 6E ntel486 processor whereas lea on 00009DC0 6C 79 20 74 61 6B 65 73 20 6F 6E 65 2E 20 20 4F 6E 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 72 ly takes one. On the Pentium pr 00009DE0 6F 63 65 73 73 6F 72 2C 20 6C 65 61 20 63 61 6E 20 65 78 65 63 75 74 65 20 69 6E 20 65 69 74 68 ocessor, lea can execute in eith 00009E00 65 72 20 55 20 6F 72 20 56 20 70 69 70 65 73 2C 20 62 75 74 20 74 68 65 20 73 68 69 66 74 20 69 er U or V pipes, but the shift i 00009E20 6E 73 74 72 75 63 74 69 6F 6E 73 20 63 61 6E 20 6F 6E 6C 79 20 65 78 65 63 75 74 65 20 69 6E 20 nstructions can only execute in 00009E40 74 68 65 20 55 20 70 69 70 65 2E 20 0D 0A 0D 0A 43 6F 6D 70 6C 65 78 20 69 6E 73 74 72 75 63 74 the U pipe. ♪◙♪◙Complex instruct 00009E60 69 6F 6E 73 0D 0A 0D 0A 41 76 6F 69 64 20 75 73 69 6E 67 20 63 6F 6D 70 6C 65 78 20 69 6E 73 74 ions♪◙♪◙Avoid using complex inst 00009E80 72 75 63 74 69 6F 6E 73 20 28 66 6F 72 20 65 78 61 6D 70 6C 65 2C 20 65 6E 74 65 72 2C 20 6C 65 ructions (for example, enter, le 00009EA0 61 76 65 2C 20 6C 6F 6F 70 29 2E 20 20 55 73 65 20 73 65 71 75 65 6E 63 65 73 20 6F 66 20 73 69 ave, loop). Use sequences of si 00009EC0 6D 70 6C 65 0D 0A 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 69 6E 73 74 65 61 64 2E 0D 0A 0D 0A 5A mple♪◙instructions instead.♪◙♪◙Z 00009EE0 65 72 6F 2D 45 78 74 65 6E 73 69 6F 6E 20 6F 66 20 53 68 6F 72 74 0D 0A 0D 0A 54 68 65 20 6D 6F ero-Extension of Short♪◙♪◙The mo 00009F00 76 7A 78 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 68 61 73 20 61 20 70 72 65 66 69 78 20 61 6E 64 vzx instruction has a prefix and 00009F20 20 74 61 6B 65 73 20 33 20 63 79 63 6C 65 73 20 74 6F 20 65 78 65 63 75 74 65 2C 20 74 6F 74 61 takes 3 cycles to execute, tota 00009F40 6C 69 6E 67 20 34 20 63 79 63 6C 65 73 2E 20 41 73 20 77 69 74 68 20 74 68 65 20 49 6E 74 65 6C ling 4 cycles. As with the Intel 00009F60 34 38 36 20 70 72 6F 63 65 73 73 6F 72 2C 20 69 74 20 69 73 20 72 65 63 6F 6D 6D 65 6E 64 65 64 486 processor, it is recommended 00009F80 20 74 68 65 20 66 6F 6C 6C 6F 77 69 6E 67 20 73 65 71 75 65 6E 63 65 20 62 65 20 75 73 65 64 20 the following sequence be used 00009FA0 69 6E 73 74 65 61 64 3A 0D 0A 0D 0A 78 6F 72 20 20 65 61 78 2C 20 65 61 78 0D 0A 6D 6F 76 20 20 instead:♪◙♪◙xor eax, eax♪◙mov 00009FC0 61 6C 2C 20 6D 65 6D 0D 0A 0D 0A 49 66 20 74 68 69 73 20 6F 63 63 75 72 73 20 77 69 74 68 69 6E al, mem♪◙♪◙If this occurs within 00009FE0 20 61 20 6C 6F 6F 70 2C 20 69 74 20 6D 61 79 20 62 65 20 70 6F 73 73 69 62 6C 65 20 74 6F 20 70 a loop, it may be possible to p 0000A000 75 6C 6C 20 74 68 65 20 78 6F 72 20 6F 75 74 20 6F 66 20 74 68 65 20 6C 6F 6F 70 20 69 66 20 74 ull the xor out of the loop if t 0000A020 68 65 20 6F 6E 6C 79 20 61 73 73 69 67 6E 6D 65 6E 74 20 74 6F 20 65 61 78 20 69 73 20 74 68 65 he only assignment to eax is the 0000A040 20 6D 6F 76 20 61 6C 2C 20 6D 65 6D 2E 20 54 68 69 73 20 68 61 73 20 67 72 65 61 74 65 72 20 69 mov al, mem. This has greater i 0000A060 6D 70 6F 72 74 61 6E 63 65 20 66 6F 72 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 mportance for the Pentium proces 0000A080 73 6F 72 20 73 69 6E 63 65 20 74 68 65 20 6D 6F 76 7A 78 20 69 73 20 6E 6F 74 20 70 61 69 72 61 sor since the movzx is not paira 0000A0A0 62 6C 65 20 61 6E 64 20 74 68 65 20 6E 65 77 20 73 65 71 75 65 6E 63 65 20 6D 61 79 20 62 65 20 ble and the new sequence may be 0000A0C0 70 61 69 72 65 64 20 77 69 74 68 20 61 64 6A 61 63 65 6E 74 20 69 6E 73 74 72 75 63 74 69 6F 6E paired with adjacent instruction 0000A0E0 73 2E 0D 0A 0D 0A 50 75 73 68 20 6D 65 6D 0D 0A 0D 0A 54 68 65 20 70 75 73 68 20 6D 65 6D 20 69 s.♪◙♪◙Push mem♪◙♪◙The push mem i 0000A100 6E 73 74 72 75 63 74 69 6F 6E 20 74 61 6B 65 73 20 66 6F 75 72 20 63 79 63 6C 65 73 20 66 6F 72 nstruction takes four cycles for 0000A120 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 2E 20 49 74 20 69 73 20 72 the Intel486 processor. It is r 0000A140 65 63 6F 6D 6D 65 6E 64 65 64 20 74 6F 20 75 73 65 20 74 68 65 20 66 6F 6C 6C 6F 77 69 6E 67 20 ecommended to use the following 0000A160 73 65 71 75 65 6E 63 65 20 62 65 63 61 75 73 65 20 69 74 20 74 61 6B 65 73 20 6F 6E 6C 79 20 74 sequence because it takes only t 0000A180 77 6F 20 63 79 63 6C 65 73 20 66 6F 72 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 wo cycles for the Intel486 proce 0000A1A0 73 73 6F 72 20 61 6E 64 20 69 6E 63 72 65 61 73 65 73 20 70 61 69 72 69 6E 67 20 6F 70 70 6F 72 ssor and increases pairing oppor 0000A1C0 74 75 6E 69 74 79 20 66 6F 72 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 tunity for the Pentium processor 0000A1E0 2E 0D 0A 0D 0A 6D 6F 76 20 20 6D 65 6D 2C 20 72 65 67 0D 0A 70 75 73 68 20 72 65 67 0D 0A 0D 0A .♪◙♪◙mov mem, reg♪◙push reg♪◙♪◙ 0000A200 53 68 6F 72 74 20 4F 70 63 6F 64 65 73 0D 0A 0D 0A 55 73 65 20 6F 6E 65 2D 62 79 74 65 20 6C 6F Short Opcodes♪◙♪◙Use one-byte lo 0000A220 6E 67 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 61 73 20 6D 75 63 68 20 61 73 20 70 6F 73 73 69 ng instructions as much as possi 0000A240 62 6C 65 2E 20 54 68 69 73 20 77 69 6C 6C 20 72 65 64 75 63 65 20 63 6F 64 65 20 73 69 7A 65 20 ble. This will reduce code size 0000A260 61 6E 64 20 68 65 6C 70 20 69 6E 63 72 65 61 73 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 64 65 and help increase instruction de 0000A280 6E 73 69 74 79 20 69 6E 20 74 68 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 63 61 63 68 65 2E 20 nsity in the instruction cache. 0000A2A0 54 68 65 20 6D 6F 73 74 20 63 6F 6D 6D 6F 6E 20 65 78 61 6D 70 6C 65 20 69 73 20 75 73 69 6E 67 The most common example is using 0000A2C0 20 69 6E 63 20 61 6E 64 20 64 65 63 20 72 61 74 68 65 72 20 74 68 61 6E 20 61 64 64 69 6E 67 20 inc and dec rather than adding 0000A2E0 6F 72 20 73 75 62 74 72 61 63 74 69 6E 67 20 74 68 65 20 63 6F 6E 73 74 61 6E 74 20 31 20 77 69 or subtracting the constant 1 wi 0000A300 74 68 20 61 64 64 20 6F 72 20 73 75 62 2E 0D 0A 0D 0A 38 2F 31 36 20 62 69 74 20 6F 70 65 72 61 th add or sub.♪◙♪◙8/16 bit opera 0000A320 6E 64 73 0D 0A 0D 0A 57 69 74 68 20 38 2D 62 69 74 20 6F 70 65 72 61 6E 64 73 2C 20 74 72 79 20 nds♪◙♪◙With 8-bit operands, try 0000A340 74 6F 20 75 73 65 20 74 68 65 20 62 79 74 65 20 6F 70 63 6F 64 65 73 2C 20 72 61 74 68 65 72 20 to use the byte opcodes, rather 0000A360 74 68 61 6E 20 75 73 69 6E 67 20 33 32 2D 62 69 74 20 6F 70 65 72 61 74 69 6F 6E 73 20 6F 6E 20 than using 32-bit operations on 0000A380 73 69 67 6E 20 61 6E 64 20 7A 65 72 6F 20 65 78 74 65 6E 64 65 64 20 62 79 74 65 73 2E 20 50 72 sign and zero extended bytes. Pr 0000A3A0 65 66 69 78 65 73 20 66 6F 72 20 6F 70 65 72 61 6E 64 20 73 69 7A 65 20 6F 76 65 72 72 69 64 65 efixes for operand size override 0000A3C0 20 61 70 70 6C 79 20 74 6F 20 31 36 2D 62 69 74 20 6F 70 65 72 61 6E 64 73 2C 20 6E 6F 74 20 74 apply to 16-bit operands, not t 0000A3E0 6F 20 38 2D 62 69 74 20 6F 70 65 72 61 6E 64 73 2E 0D 0A 0D 0A 53 69 67 6E 20 45 78 74 65 6E 73 o 8-bit operands.♪◙♪◙Sign Extens 0000A400 69 6F 6E 20 69 73 20 75 73 75 61 6C 6C 79 20 71 75 69 74 65 20 65 78 70 65 6E 73 69 76 65 2E 20 ion is usually quite expensive. 0000A420 4F 66 74 65 6E 2C 20 74 68 65 20 73 65 6D 61 6E 74 69 63 73 20 63 61 6E 20 62 65 20 6D 61 69 6E Often, the semantics can be main 0000A440 74 61 69 6E 65 64 20 62 79 20 7A 65 72 6F 20 65 78 74 65 6E 64 69 6E 67 20 31 36 2D 62 69 74 20 tained by zero extending 16-bit 0000A460 6F 70 65 72 61 6E 64 73 2E 20 53 70 65 63 69 66 69 63 61 6C 6C 79 2C 20 74 68 65 20 43 20 63 6F operands. Specifically, the C co 0000A480 64 65 20 69 6E 20 74 68 65 20 66 6F 6C 6C 6F 77 69 6E 67 20 65 78 61 6D 70 6C 65 20 64 6F 65 73 de in the following example does 0000A4A0 20 6E 6F 74 20 6E 65 65 64 20 73 69 67 6E 20 65 78 74 65 6E 73 69 6F 6E 20 6E 6F 72 20 64 6F 65 not need sign extension nor doe 0000A4C0 73 20 69 74 20 6E 65 65 64 20 70 72 65 66 69 78 65 73 20 66 6F 72 20 6F 70 65 72 61 6E 64 20 73 s it need prefixes for operand s 0000A4E0 69 7A 65 20 6F 76 65 72 72 69 64 65 73 2E 0D 0A 0D 0A 73 74 61 74 69 63 20 73 68 6F 72 74 20 69 ize overrides.♪◙♪◙static short i 0000A500 6E 74 20 61 2C 20 62 3B 0D 0A 69 66 20 28 61 3D 3D 62 29 20 7B 0D 0A 20 20 20 2E 20 2E 20 2E 0D nt a, b;♪◙if (a==b) {♪◙ . . .♪ 0000A520 0A 7D 0D 0A 0D 0A 43 6F 64 65 20 66 6F 72 20 63 6F 6D 70 61 72 69 6E 67 20 74 68 65 73 65 20 31 ◙}♪◙♪◙Code for comparing these 1 0000A540 36 2D 62 69 74 20 6F 70 65 72 61 6E 64 73 20 6D 69 67 68 74 20 62 65 3A 0D 0A 0D 0A 20 20 20 20 6-bit operands might be:♪◙♪◙ 0000A560 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 09 20 20 20 55 20 70 69 70 65 20 20 20 09 20 20 20 ○ U pipe ○ 0000A580 20 20 09 56 20 20 70 69 70 65 09 09 0D 0A 0D 0A 09 09 78 6F 72 20 20 65 61 78 2C 20 65 61 78 20 ○V pipe○○♪◙♪◙○○xor eax, eax 0000A5A0 09 78 6F 72 20 20 65 62 78 2C 20 65 62 78 20 20 20 20 20 20 09 3B 20 31 0D 0A 09 09 6D 6F 76 77 ○xor ebx, ebx ○; 1♪◙○○movw 0000A5C0 09 61 78 2C 20 5B 61 5D 09 09 09 09 09 3B 20 32 20 28 70 72 65 66 69 78 29 20 2B 20 31 0D 0A 09 ○ax, [a]○○○○○; 2 (prefix) + 1♪◙○ 0000A5E0 09 6D 6F 76 77 09 62 78 2C 20 5B 62 5D 09 09 09 09 09 3B 20 34 20 28 70 72 65 66 69 78 29 20 2B ○movw○bx, [b]○○○○○; 4 (prefix) + 0000A600 31 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 09 09 63 6D 70 20 20 65 61 1 ○○cmp ea 0000A620 78 2C 20 65 62 78 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 09 3B x, ebx ○; 0000A640 20 36 0D 0A 0D 0A 54 68 65 20 73 74 72 61 69 67 68 74 2D 66 6F 72 77 61 72 64 20 6D 65 74 68 6F 6♪◙♪◙The straight-forward metho 0000A660 64 20 6D 61 79 20 62 65 20 73 6C 6F 77 65 72 3A 0D 0A 0D 0A 6D 6F 76 73 77 20 09 65 61 78 2C 20 d may be slower:♪◙♪◙movsw ○eax, 0000A680 61 09 3B 20 31 20 20 31 20 70 72 65 66 69 78 20 2B 20 33 0D 0A 6D 6F 76 73 77 20 09 65 62 78 2C a○; 1 1 prefix + 3♪◙movsw ○ebx, 0000A6A0 20 62 09 3B 20 35 0D 0A 63 6D 70 20 20 20 20 09 65 62 78 2C 20 65 61 78 20 09 3B 20 39 0D 0A 0D b○; 5♪◙cmp ○ebx, eax ○; 9♪◙♪ 0000A6C0 0A 4F 66 20 63 6F 75 72 73 65 2C 20 74 68 69 73 20 63 61 6E 20 6F 6E 6C 79 20 62 65 20 64 6F 6E ◙Of course, this can only be don 0000A6E0 65 20 75 6E 64 65 72 20 63 65 72 74 61 69 6E 20 63 69 72 63 75 6D 73 74 61 6E 63 65 73 2C 20 62 e under certain circumstances, b 0000A700 75 74 20 74 68 65 20 63 69 72 63 75 6D 73 74 61 6E 63 65 73 20 74 65 6E 64 20 74 6F 20 62 65 20 ut the circumstances tend to be 0000A720 71 75 69 74 65 20 63 6F 6D 6D 6F 6E 2E 20 54 68 69 73 20 77 6F 75 6C 64 20 6E 6F 74 20 77 6F 72 quite common. This would not wor 0000A740 6B 20 69 66 20 74 68 65 20 63 6F 6D 70 61 72 65 20 77 61 73 20 66 6F 72 20 67 72 65 61 74 65 72 k if the compare was for greater 0000A760 20 74 68 61 6E 2C 20 6C 65 73 73 20 74 68 61 6E 2C 20 67 72 65 61 74 65 72 20 74 68 61 6E 20 6F than, less than, greater than o 0000A780 72 20 65 71 75 61 6C 2C 20 61 6E 64 20 73 6F 20 6F 6E 2C 20 6F 72 20 69 66 20 74 68 65 20 76 61 r equal, and so on, or if the va 0000A7A0 6C 75 65 73 20 69 6E 20 65 61 78 20 6F 72 20 65 62 78 20 77 65 72 65 20 74 6F 20 62 65 20 75 73 lues in eax or ebx were to be us 0000A7C0 65 64 20 69 6E 20 61 6E 6F 74 68 65 72 20 6F 70 65 72 61 74 69 6F 6E 20 77 68 65 72 65 20 73 69 ed in another operation where si 0000A7E0 67 6E 20 65 78 74 65 6E 73 69 6F 6E 20 77 61 73 20 72 65 71 75 69 72 65 64 2E 0D 0A 0D 0A 43 6F gn extension was required.♪◙♪◙Co 0000A800 6D 70 61 72 65 73 0D 0A 0D 0A 55 73 65 20 74 65 73 74 20 77 68 65 6E 20 63 6F 6D 70 61 72 69 6E mpares♪◙♪◙Use test when comparin 0000A820 67 20 61 20 76 61 6C 75 65 20 69 6E 20 61 20 72 65 67 69 73 74 65 72 20 77 69 74 68 20 30 2E 20 g a value in a register with 0. 0000A840 54 65 73 74 20 65 73 73 65 6E 74 69 61 6C 6C 79 20 22 61 6E 64 73 22 20 74 68 65 20 6F 70 65 72 Test essentially "ands" the oper 0000A860 61 6E 64 73 20 74 6F 67 65 74 68 65 72 20 77 69 74 68 6F 75 74 20 77 72 69 74 69 6E 67 20 74 6F ands together without writing to 0000A880 20 61 20 64 65 73 74 69 6E 61 74 69 6F 6E 20 72 65 67 69 73 74 65 72 2E 20 49 66 20 79 6F 75 20 a destination register. If you 0000A8A0 22 61 6E 64 22 20 61 20 76 61 6C 75 65 20 77 69 74 68 20 69 74 73 65 6C 66 20 61 6E 64 20 74 68 "and" a value with itself and th 0000A8C0 65 20 72 65 73 75 6C 74 20 73 65 74 73 20 74 68 65 20 7A 65 72 6F 20 63 6F 6E 64 69 74 69 6F 6E e result sets the zero condition 0000A8E0 20 66 6C 61 67 2C 20 74 68 65 20 76 61 6C 75 65 20 77 61 73 20 7A 65 72 6F 2E 20 54 65 73 74 20 flag, the value was zero. Test 0000A900 69 73 20 70 72 65 66 65 72 72 65 64 20 6F 76 65 72 20 61 6E 64 20 62 65 63 61 75 73 65 20 74 68 is preferred over and because th 0000A920 65 20 61 6E 64 20 77 72 69 74 65 73 20 74 68 65 20 72 65 73 75 6C 74 20 72 65 67 69 73 74 65 72 e and writes the result register 0000A940 20 77 68 69 63 68 20 6D 61 79 20 73 75 62 73 65 71 75 65 6E 74 6C 79 20 63 61 75 73 65 20 61 6E which may subsequently cause an 0000A960 20 41 47 49 2E 20 20 54 65 73 74 20 69 73 20 62 65 74 74 65 72 20 74 68 61 6E 20 63 6D 70 20 20 AGI. Test is better than cmp 0000A980 2E 2E 2C 20 30 20 62 65 63 61 75 73 65 20 74 68 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 73 69 .., 0 because the instruction si 0000A9A0 7A 65 20 69 73 20 73 6D 61 6C 6C 65 72 2E 0D 0A 0D 0A 55 73 65 20 74 65 73 74 20 77 68 65 6E 20 ze is smaller.♪◙♪◙Use test when 0000A9C0 63 6F 6D 70 61 72 69 6E 67 20 74 68 65 20 72 65 73 75 6C 74 20 6F 66 20 61 20 42 6F 6F 6C 65 61 comparing the result of a Boolea 0000A9E0 6E 20 22 61 6E 64 22 20 77 69 74 68 20 61 6E 20 69 6D 6D 65 64 69 61 74 65 20 63 6F 6E 73 74 61 n "and" with an immediate consta 0000AA00 6E 74 20 66 6F 72 0D 0A 65 71 75 61 6C 69 74 79 20 6F 72 20 69 6E 65 71 75 61 6C 69 74 79 20 69 nt for♪◙equality or inequality i 0000AA20 66 20 74 68 65 20 72 65 67 69 73 74 65 72 20 69 73 20 65 61 78 2E 20 28 69 66 20 28 61 76 61 72 f the register is eax. (if (avar 0000AA40 20 26 20 38 29 20 7B 20 7D 29 2E 0D 0A 0D 0A 54 65 73 74 20 69 73 20 61 20 6F 6E 65 2D 63 79 63 & 8) { }).♪◙♪◙Test is a one-cyc 0000AA60 6C 65 20 70 61 69 72 61 62 6C 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 77 68 65 6E 20 74 68 65 le pairable instruction when the 0000AA80 20 66 6F 72 6D 20 69 73 20 65 61 78 2C 20 69 6D 6D 20 6F 72 20 72 65 67 2C 20 72 65 67 2E 20 4F form is eax, imm or reg, reg. O 0000AAA0 74 68 65 72 0D 0A 66 6F 72 6D 73 20 6F 66 20 74 65 73 74 20 74 61 6B 65 20 74 77 6F 20 63 79 63 ther♪◙forms of test take two cyc 0000AAC0 6C 65 73 20 61 6E 64 20 64 6F 20 6E 6F 74 20 70 61 69 72 2E 0D 0A 0D 0A 41 64 64 72 65 73 73 20 les and do not pair.♪◙♪◙Address 0000AAE0 43 61 6C 63 75 6C 61 74 69 6F 6E 73 0D 0A 0D 0A 50 75 6C 6C 20 61 64 64 72 65 73 73 20 63 61 6C Calculations♪◙♪◙Pull address cal 0000AB00 63 75 6C 61 74 69 6F 6E 73 20 69 6E 74 6F 20 6C 6F 61 64 20 61 6E 64 20 73 74 6F 72 65 20 69 6E culations into load and store in 0000AB20 73 74 72 75 63 74 69 6F 6E 73 2E 20 49 6E 74 65 72 6E 61 6C 6C 79 2C 20 6D 65 6D 6F 72 79 20 72 structions. Internally, memory r 0000AB40 65 66 65 72 65 6E 63 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 63 61 6E 20 68 61 76 65 20 34 eference instructions can have 4 0000AB60 20 6F 70 65 72 61 6E 64 73 3A 20 61 20 72 65 6C 6F 63 61 74 61 62 6C 65 20 6C 6F 61 64 2D 74 69 operands: a relocatable load-ti 0000AB80 6D 65 20 63 6F 6E 73 74 61 6E 74 2C 20 61 6E 20 69 6D 6D 65 64 69 61 74 65 20 63 6F 6E 73 74 61 me constant, an immediate consta 0000ABA0 6E 74 2C 20 61 20 62 61 73 65 20 72 65 67 69 73 74 65 72 2C 20 61 6E 64 20 61 20 73 63 61 6C 65 nt, a base register, and a scale 0000ABC0 64 20 69 6E 64 65 78 20 72 65 67 69 73 74 65 72 2E 20 28 49 6E 20 74 68 65 20 73 65 67 6D 65 6E d index register. (In the segmen 0000ABE0 74 65 64 20 6D 6F 64 65 6C 2C 20 61 20 73 65 67 6D 65 6E 74 20 72 65 67 69 73 74 65 72 20 6D 61 ted model, a segment register ma 0000AC00 79 20 63 6F 6E 73 74 69 74 75 74 65 20 61 6E 20 61 64 64 69 74 69 6F 6E 61 6C 20 6F 70 65 72 61 y constitute an additional opera 0000AC20 6E 64 20 69 6E 20 74 68 65 20 6C 69 6E 65 61 72 20 61 64 64 72 65 73 73 20 63 61 6C 63 75 6C 61 nd in the linear address calcula 0000AC40 74 69 6F 6E 2E 29 20 49 6E 20 6D 61 6E 79 20 63 61 73 65 73 2C 20 73 65 76 65 72 61 6C 20 69 6E tion.) In many cases, several in 0000AC60 74 65 67 65 72 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 63 61 6E 20 62 65 20 65 6C 69 6D 69 6E teger instructions can be elimin 0000AC80 61 74 65 64 20 62 79 20 66 75 6C 6C 79 20 75 73 69 6E 67 20 74 68 65 20 6F 70 65 72 61 6E 64 73 ated by fully using the operands 0000ACA0 20 6F 66 20 6D 65 6D 6F 72 79 20 72 65 66 65 72 65 6E 63 65 73 2E 0D 0A 0D 0A 57 68 65 6E 20 74 of memory references.♪◙♪◙When t 0000ACC0 68 65 72 65 20 69 73 20 61 20 63 68 6F 69 63 65 20 74 6F 20 75 73 65 20 65 69 74 68 65 72 20 61 here is a choice to use either a 0000ACE0 20 62 61 73 65 20 6F 72 20 69 6E 64 65 78 20 72 65 67 69 73 74 65 72 2C 20 61 6C 77 61 79 73 20 base or index register, always 0000AD00 63 68 6F 6F 73 65 20 74 68 65 20 62 61 73 65 20 62 65 63 61 75 73 65 20 74 68 65 72 65 20 69 73 choose the base because there is 0000AD20 20 61 20 31 2D 63 6C 6F 63 6B 20 70 65 6E 61 6C 74 79 20 6F 6E 20 74 68 65 20 49 6E 74 65 6C 34 a 1-clock penalty on the Intel4 0000AD40 38 36 20 70 72 6F 63 65 73 73 6F 72 20 66 6F 72 20 75 73 69 6E 67 20 61 6E 20 69 6E 64 65 78 2E 86 processor for using an index. 0000AD60 0D 0A 0D 0A 43 6C 65 61 72 69 6E 67 20 61 20 52 65 67 69 73 74 65 72 0D 0A 0D 0A 54 68 65 20 70 ♪◙♪◙Clearing a Register♪◙♪◙The p 0000AD80 72 65 66 65 72 72 65 64 20 73 65 71 75 65 6E 63 65 20 74 6F 20 6D 6F 76 65 20 7A 65 72 6F 20 74 referred sequence to move zero t 0000ADA0 6F 20 61 20 72 65 67 69 73 74 65 72 20 69 73 20 78 6F 72 20 72 65 67 2C 20 72 65 67 2E 20 54 68 o a register is xor reg, reg. Th 0000ADC0 69 73 20 73 61 76 65 73 20 63 6F 64 65 20 73 70 61 63 65 20 62 75 74 20 73 65 74 73 20 74 68 65 is saves code space but sets the 0000ADE0 20 63 6F 6E 64 69 74 69 6F 6E 20 63 6F 64 65 73 2E 20 49 6E 20 63 6F 6E 74 65 78 74 73 20 77 68 condition codes. In contexts wh 0000AE00 65 72 65 20 74 68 65 20 63 6F 6E 64 69 74 69 6F 6E 20 63 6F 64 65 73 20 6D 75 73 74 20 62 65 20 ere the condition codes must be 0000AE20 70 72 65 73 65 72 76 65 64 2C 20 75 73 65 20 6D 6F 76 20 72 65 67 2C 20 30 2E 0D 0A 0D 0A 49 6E preserved, use mov reg, 0.♪◙♪◙In 0000AE40 74 65 67 65 72 20 44 69 76 69 64 65 0D 0A 0D 0A 54 79 70 69 63 61 6C 6C 79 2C 20 61 6E 20 69 6E teger Divide♪◙♪◙Typically, an in 0000AE60 74 65 67 65 72 20 64 69 76 69 64 65 20 69 73 20 70 72 65 63 65 64 65 64 20 62 79 20 61 20 63 64 teger divide is preceded by a cd 0000AE80 71 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 28 44 69 76 69 64 65 20 69 6E 73 74 72 75 63 74 69 6F q instruction (Divide instructio 0000AEA0 6E 73 20 75 73 65 20 65 64 78 3A 20 65 61 78 20 61 73 20 74 68 65 20 64 69 76 69 64 65 6E 64 20 ns use edx: eax as the dividend 0000AEC0 61 6E 64 20 63 64 71 20 73 65 74 73 20 75 70 20 65 64 78 29 2E 20 49 74 20 69 73 20 62 65 74 74 and cdq sets up edx). It is bett 0000AEE0 65 72 20 74 6F 20 63 6F 70 79 20 65 61 78 20 69 6E 74 6F 20 65 64 78 2C 20 74 68 65 6E 20 72 69 er to copy eax into edx, then ri 0000AF00 67 68 74 20 73 68 69 66 74 20 65 64 78 20 33 31 20 70 6C 61 63 65 73 20 74 6F 20 73 69 67 6E 20 ght shift edx 31 places to sign 0000AF20 65 78 74 65 6E 64 2E 20 54 68 65 20 63 6F 70 79 2F 73 68 69 66 74 20 74 61 6B 65 73 20 74 68 65 extend. The copy/shift takes the 0000AF40 20 73 61 6D 65 20 6E 75 6D 62 65 72 20 6F 66 20 63 6C 6F 63 6B 73 20 61 73 20 63 64 71 20 6F 6E same number of clocks as cdq on 0000AF60 20 62 6F 74 68 20 74 68 65 20 50 65 6E 74 69 75 6D 20 61 6E 64 20 49 6E 74 65 6C 34 38 36 20 70 both the Pentium and Intel486 p 0000AF80 72 6F 63 65 73 73 6F 72 73 2C 20 62 75 74 20 74 68 65 20 63 6F 70 79 2F 73 68 69 66 74 20 20 73 rocessors, but the copy/shift s 0000AFA0 63 68 65 6D 65 20 61 6C 6C 6F 77 73 20 74 77 6F 20 6F 74 68 65 72 20 69 6E 73 74 72 75 63 74 69 cheme allows two other instructi 0000AFC0 6F 6E 73 20 74 6F 20 65 78 65 63 75 74 65 20 61 74 20 74 68 65 20 73 61 6D 65 20 74 69 6D 65 20 ons to execute at the same time 0000AFE0 6F 6E 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 2E 20 20 49 66 20 79 6F on the Pentium processor. If yo 0000B000 75 20 6B 6E 6F 77 20 74 68 65 20 76 61 6C 75 65 20 69 73 20 70 6F 73 69 74 69 76 65 2C 20 75 73 u know the value is positive, us 0000B020 65 20 78 6F 72 20 65 64 78 2C 20 65 64 78 2E 0D 0A 0D 0A 50 72 6F 6C 6F 67 20 53 65 71 75 65 6E e xor edx, edx.♪◙♪◙Prolog Sequen 0000B040 63 65 73 0D 0A 0D 0A 42 65 20 63 61 72 65 66 75 6C 20 74 6F 20 61 76 6F 69 64 20 41 47 6C 27 73 ces♪◙♪◙Be careful to avoid AGl's 0000B060 20 69 6E 20 74 68 65 20 70 72 6F 6C 6F 67 20 64 75 65 20 74 6F 20 72 65 67 69 73 74 65 72 20 65 in the prolog due to register e 0000B080 73 70 2E 20 53 69 6E 63 65 20 70 75 73 68 20 63 61 6E 20 70 61 69 72 20 77 69 74 68 20 6F 74 68 sp. Since push can pair with oth 0000B0A0 65 72 20 70 75 73 68 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 2C 20 73 61 76 69 6E 67 20 63 61 6C er push instructions, saving cal 0000B0C0 6C 65 65 2D 73 61 76 65 64 20 72 65 67 69 73 74 65 72 73 20 6F 6E 20 65 6E 74 72 79 20 74 6F 20 lee-saved registers on entry to 0000B0E0 66 75 6E 63 74 69 6F 6E 73 20 73 68 6F 75 6C 64 20 75 73 65 20 74 68 65 73 65 20 69 6E 73 74 72 functions should use these instr 0000B100 75 63 74 69 6F 6E 73 2E 20 49 66 20 70 6F 73 73 69 62 6C 65 2C 20 6C 6F 61 64 20 70 61 72 61 6D uctions. If possible, load param 0000B120 65 74 65 72 73 20 62 65 66 6F 72 65 20 64 65 63 72 65 6D 65 6E 74 69 6E 67 20 65 73 70 2E 0D 0A eters before decrementing esp.♪◙ 0000B140 0D 0A 49 6E 20 20 72 6F 75 74 69 6E 65 73 20 74 68 61 74 20 64 6F 20 6E 6F 74 20 63 61 6C 6C 20 ♪◙In routines that do not call 0000B160 6F 74 68 65 72 20 72 6F 75 74 69 6E 65 73 20 28 6C 65 61 66 20 72 6F 75 74 69 6E 65 73 29 2C 20 other routines (leaf routines), 0000B180 75 73 65 20 65 73 70 20 61 73 20 74 68 65 20 62 61 73 65 20 72 65 67 69 73 74 65 72 20 74 6F 20 use esp as the base register to 0000B1A0 66 72 65 65 20 75 70 20 65 62 70 2E 20 49 66 20 79 6F 75 20 61 72 65 20 6E 6F 74 20 75 73 69 6E free up ebp. If you are not usin 0000B1C0 67 20 74 68 65 20 33 32 2D 62 69 74 20 66 6C 61 74 20 6D 6F 64 65 6C 2C 20 20 72 65 6D 65 6D 62 g the 32-bit flat model, rememb 0000B1E0 65 72 20 74 68 61 74 20 65 62 70 20 63 61 6E 6E 6F 74 20 62 65 20 75 73 65 64 20 61 73 20 61 20 er that ebp cannot be used as a 0000B200 67 65 6E 65 72 61 6C 20 70 75 72 70 6F 73 65 20 62 61 73 65 20 72 65 67 69 73 74 65 72 20 62 65 general purpose base register be 0000B220 63 61 75 73 65 20 69 74 20 72 65 66 65 72 65 6E 63 65 73 20 74 68 65 20 73 74 61 63 6B 20 73 65 cause it references the stack se 0000B240 67 6D 65 6E 74 2E 0D 0A 0D 0A 41 76 6F 69 64 20 43 6F 6D 70 61 72 65 73 20 77 69 74 68 20 49 6D gment.♪◙♪◙Avoid Compares with Im 0000B260 6D 65 64 69 61 74 65 20 5A 65 72 6F 0D 0A 0D 0A 4F 66 74 65 6E 20 77 68 65 6E 20 61 20 76 61 6C mediate Zero♪◙♪◙Often when a val 0000B280 75 65 20 69 73 20 63 6F 6D 70 61 72 65 64 20 77 69 74 68 20 7A 65 72 6F 2C 20 74 68 65 20 6F 70 ue is compared with zero, the op 0000B2A0 65 72 61 74 69 6F 6E 20 70 72 6F 64 75 63 69 6E 67 20 74 68 65 20 76 61 6C 75 65 20 73 65 74 73 eration producing the value sets 0000B2C0 20 63 6F 6E 64 69 74 69 6F 6E 20 63 6F 64 65 73 20 77 68 69 63 68 20 63 61 6E 20 62 65 20 74 65 condition codes which can be te 0000B2E0 73 74 65 64 20 64 69 72 65 63 74 6C 79 20 62 79 20 61 20 6A 63 63 20 69 6E 73 74 72 75 63 74 69 sted directly by a jcc instructi 0000B300 6F 6E 2E 20 54 68 65 20 6D 6F 73 74 20 6E 6F 74 61 62 6C 65 20 65 78 63 65 70 74 69 6F 6E 73 20 on. The most notable exceptions 0000B320 61 72 65 20 6D 6F 76 20 61 6E 64 20 6C 65 61 2E 20 49 6E 20 74 68 65 73 65 20 63 61 73 65 73 2C are mov and lea. In these cases, 0000B340 20 75 73 65 20 74 65 73 74 2E 0D 0A 0D 0A 45 70 69 6C 6F 67 20 53 65 71 75 65 6E 63 65 0D 0A 0D use test.♪◙♪◙Epilog Sequence♪◙♪ 0000B360 0A 49 66 20 6F 6E 6C 79 20 34 20 62 79 74 65 73 20 77 65 72 65 20 61 6C 6C 6F 63 61 74 65 64 20 ◙If only 4 bytes were allocated 0000B380 69 6E 20 74 68 65 20 73 74 61 63 6B 20 66 72 61 6D 65 20 66 6F 72 20 74 68 65 20 63 75 72 72 65 in the stack frame for the curre 0000B3A0 6E 74 20 66 75 6E 63 74 69 6F 6E 2C 20 69 6E 73 74 65 61 64 20 6F 66 20 69 6E 63 72 65 6D 65 6E nt function, instead of incremen 0000B3C0 74 69 6E 67 20 74 68 65 20 73 74 61 63 6B 20 70 6F 69 6E 74 65 72 20 62 79 20 34 2C 20 75 73 65 ting the stack pointer by 4, use 0000B3E0 20 70 6F 70 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 2E 20 54 68 69 73 20 61 76 6F 69 64 73 20 41 pop instructions. This avoids A 0000B400 47 6C 73 20 61 6E 64 20 68 65 6C 70 73 20 62 6F 74 68 20 49 6E 74 65 6C 34 38 36 20 61 6E 64 20 Gls and helps both Intel486 and 0000B420 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 2E 20 20 46 6F 72 20 50 65 6E 74 69 75 6D 20 Pentium processor. For Pentium 0000B440 70 72 6F 63 65 73 73 6F 72 20 75 73 65 20 32 20 70 6F 70 73 20 66 6F 72 20 65 69 67 68 74 20 62 processor use 2 pops for eight b 0000B460 79 74 65 73 2E 0D 0A 0D 0A 49 6E 74 65 67 65 72 20 4D 75 6C 74 69 70 6C 79 20 62 79 20 43 6F 6E ytes.♪◙♪◙Integer Multiply by Con 0000B480 73 74 61 6E 74 20 0D 0A 0D 0A 54 68 65 20 69 6E 74 65 67 65 72 20 6D 75 6C 74 69 70 6C 79 20 62 stant ♪◙♪◙The integer multiply b 0000B4A0 79 20 61 6E 20 69 6D 6D 65 64 69 61 74 65 20 63 61 6E 20 75 73 75 61 6C 6C 79 20 62 65 20 72 65 y an immediate can usually be re 0000B4C0 70 6C 61 63 65 64 20 62 79 20 61 20 66 61 73 74 65 72 20 73 65 72 69 65 73 20 6F 66 20 73 68 69 placed by a faster series of shi 0000B4E0 66 74 73 2C 20 61 64 64 73 2C 20 73 75 62 73 2C 20 61 6E 64 20 6C 65 61 73 2E 0D 0A 0D 0A 61 2E fts, adds, subs, and leas.♪◙♪◙a. 0000B500 20 42 69 6E 61 72 79 20 4D 65 74 68 6F 64 0D 0A 0D 0A 49 6E 20 67 65 6E 65 72 61 6C 2C 20 69 66 Binary Method♪◙♪◙In general, if 0000B520 20 74 68 65 72 65 20 61 72 65 20 38 20 6F 72 20 66 65 77 65 72 20 62 69 74 73 20 73 65 74 20 69 there are 8 or fewer bits set i 0000B540 6E 20 74 68 65 20 62 69 6E 61 72 79 20 72 65 70 72 65 73 65 6E 74 61 74 69 6F 6E 20 6F 66 20 74 n the binary representation of t 0000B560 68 65 20 63 6F 6E 73 74 61 6E 74 2C 20 69 74 20 69 73 20 62 65 74 74 65 72 20 6E 6F 74 20 74 6F he constant, it is better not to 0000B580 20 64 6F 20 74 68 65 20 69 6E 74 65 67 65 72 20 6D 75 6C 74 69 70 6C 79 2E 20 4F 6E 20 61 6E 20 do the integer multiply. On an 0000B5A0 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 2C 20 74 68 65 20 62 72 65 61 6B 20 65 76 Intel486 processor, the break ev 0000B5C0 65 6E 20 70 6F 69 6E 74 20 69 73 20 6C 6F 77 65 72 3A 20 69 74 20 69 73 20 70 72 6F 66 69 74 61 en point is lower: it is profita 0000B5E0 62 6C 65 20 69 66 20 36 20 62 69 74 73 20 6F 72 20 6C 65 73 73 20 61 72 65 20 69 6E 20 74 68 65 ble if 6 bits or less are in the 0000B600 20 63 6F 6E 73 74 61 6E 74 2E 20 42 61 73 69 63 61 6C 6C 79 2C 20 73 68 69 66 74 20 61 6E 64 20 constant. Basically, shift and 0000B620 61 64 64 20 66 6F 72 20 65 61 63 68 20 62 69 74 20 73 65 74 2E 0D 0A 0D 0A 62 2E 20 46 61 63 74 add for each bit set.♪◙♪◙b. Fact 0000B640 6F 72 69 7A 61 74 69 6F 6E 20 4D 65 74 68 6F 64 0D 0A 0D 0A 54 68 69 73 20 69 73 20 64 6F 6E 65 orization Method♪◙♪◙This is done 0000B660 20 62 79 20 66 61 63 74 6F 72 69 6E 67 20 74 68 65 20 63 6F 6E 73 74 61 6E 74 20 62 79 20 70 6F by factoring the constant by po 0000B680 77 65 72 73 20 6F 66 20 74 77 6F 20 70 6C 75 73 20 6F 72 20 6D 69 6E 75 73 20 6F 6E 65 2C 20 61 wers of two plus or minus one, a 0000B6A0 6E 64 20 74 68 65 20 63 6F 6E 73 74 61 6E 74 20 70 6C 75 73 20 6F 72 20 6D 69 6E 75 73 20 6F 6E nd the constant plus or minus on 0000B6C0 65 20 62 79 20 70 6F 77 65 72 73 20 6F 66 20 74 77 6F 2E 20 49 66 20 74 68 65 20 6E 75 6D 62 65 e by powers of two. If the numbe 0000B6E0 72 20 63 61 6E 20 62 65 20 66 61 63 74 6F 72 65 64 20 62 79 20 70 6F 77 65 72 73 20 6F 66 20 74 r can be factored by powers of t 0000B700 77 6F 2C 20 74 68 65 6E 20 74 68 65 20 6D 75 6C 74 69 70 6C 69 63 61 74 69 6F 6E 20 63 61 6E 20 wo, then the multiplication can 0000B720 62 65 20 70 65 72 66 6F 72 6D 65 64 20 62 79 20 61 20 73 65 72 69 65 73 20 6F 66 20 73 68 69 66 be performed by a series of shif 0000B740 74 73 2E 20 49 66 20 70 6F 77 65 72 73 20 6F 66 20 74 77 6F 20 70 6C 75 73 20 6F 72 20 6D 69 6E ts. If powers of two plus or min 0000B760 75 73 20 6F 6E 65 20 61 72 65 20 69 6E 63 6C 75 64 65 64 2C 20 61 20 73 68 69 66 74 20 6F 66 20 us one are included, a shift of 0000B780 74 68 65 20 70 72 65 76 69 6F 75 73 0D 0A 72 65 73 75 6C 74 20 61 6E 64 20 61 6E 20 61 64 64 20 the previous♪◙result and an add 0000B7A0 6F 72 20 73 75 62 74 72 61 63 74 20 6F 66 20 74 68 65 20 70 72 65 76 69 6F 75 73 20 72 65 73 75 or subtract of the previous resu 0000B7C0 6C 74 20 63 61 6E 20 62 65 20 67 65 6E 65 72 61 74 65 64 2E 20 20 49 66 20 74 68 65 20 67 69 76 lt can be generated. If the giv 0000B7E0 65 6E 20 6E 75 6D 62 65 72 20 70 6C 75 73 20 6F 72 20 6D 69 6E 75 73 20 6F 6E 65 20 63 61 6E 20 en number plus or minus one can 0000B800 62 65 20 66 61 63 74 6F 72 65 64 20 62 79 20 61 20 70 6F 77 65 72 20 6F 66 20 74 77 6F 2C 20 61 be factored by a power of two, a 0000B820 20 73 68 69 66 74 20 6F 66 20 74 68 65 20 70 72 65 76 69 6F 75 73 20 72 65 73 75 6C 74 20 61 6E shift of the previous result an 0000B840 64 20 61 6E 20 61 64 64 20 6F 72 20 73 75 62 74 72 61 63 74 20 6F 66 20 74 68 65 20 6F 72 69 67 d an add or subtract of the orig 0000B860 69 6E 61 6C 20 6F 70 65 72 61 6E 64 20 63 61 6E 20 62 65 20 67 65 6E 65 72 61 74 65 64 2E 20 20 inal operand can be generated. 0000B880 20 41 6E 20 69 74 65 72 61 74 69 76 65 20 66 6F 72 20 63 68 65 63 6B 69 6E 67 20 70 6F 77 65 72 An iterative for checking power 0000B8A0 73 20 6F 66 20 74 77 6F 20 66 72 6F 6D 20 33 31 20 74 6F 20 31 20 63 61 6E 20 62 65 20 64 6F 6E s of two from 31 to 1 can be don 0000B8C0 65 2E 20 20 54 68 65 20 73 68 69 66 74 20 61 6D 6F 75 6E 74 20 6E 65 65 64 65 64 20 61 6E 64 20 e. The shift amount needed and 0000B8E0 61 6E 20 6F 72 64 69 6E 61 6C 20 74 6F 20 73 70 65 63 69 66 79 20 61 6E 20 61 64 64 20 6F 72 20 an ordinal to specify an add or 0000B900 73 75 62 74 72 61 63 74 20 69 73 20 73 61 76 65 64 20 66 6F 72 20 65 61 63 68 20 66 61 63 74 6F subtract is saved for each facto 0000B920 72 2E 20 54 68 69 73 20 69 6E 66 6F 72 6D 61 74 69 6F 6E 20 63 61 6E 20 62 65 20 75 73 65 64 20 r. This information can be used 0000B940 69 6E 20 72 65 76 65 72 73 65 20 6F 72 64 65 72 20 74 6F 20 67 65 6E 65 72 61 74 65 20 74 68 65 in reverse order to generate the 0000B960 20 6E 65 65 64 65 64 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 2E 0D 0A 0D 0A 46 6F 72 20 65 78 61 needed instructions.♪◙♪◙For exa 0000B980 6D 70 6C 65 3A 0D 0A 0D 0A 69 6D 75 6C 20 20 65 61 78 2C 20 32 31 37 20 20 20 20 20 20 3B 20 31 mple:♪◙♪◙imul eax, 217 ; 1 0000B9A0 30 20 63 6C 6F 63 6B 73 2C 20 6E 6F 20 70 61 69 72 69 6E 67 0D 0A 0D 0A 49 6E 20 63 68 65 63 6B 0 clocks, no pairing♪◙♪◙In check 0000B9C0 69 6E 67 20 70 6F 77 65 72 73 20 6F 66 20 74 77 6F 20 69 6E 20 64 65 63 72 65 61 73 69 6E 67 20 ing powers of two in decreasing 0000B9E0 6F 72 64 65 72 20 20 69 74 20 69 73 20 66 6F 75 6E 64 20 74 68 61 74 20 32 31 37 20 77 69 6C 6C order it is found that 217 will 0000BA00 20 64 69 76 69 64 65 20 62 79 20 33 31 2E 0D 0A 20 20 20 20 20 20 32 31 37 2F 33 31 20 3D 20 37 divide by 31.♪◙ 217/31 = 7 0000BA20 2E 20 20 20 20 20 20 20 33 31 20 3D 20 28 32 5E 5E 35 29 2D 31 0D 0A 0D 0A 73 61 76 65 20 73 68 . 31 = (2^^5)-1♪◙♪◙save sh 0000BA40 69 66 74 20 3D 20 35 20 61 6E 64 20 6F 72 64 69 6E 61 6C 20 3D 20 73 75 62 5F 70 72 65 76 69 6F ift = 5 and ordinal = sub_previo 0000BA60 75 73 5F 72 65 73 75 6C 74 0D 0A 0D 0A 41 66 74 65 72 20 61 20 63 68 65 63 6B 20 6F 66 20 32 31 us_result♪◙♪◙After a check of 21 0000BA80 37 2F 33 31 20 6F 72 20 37 2C 20 69 74 20 69 73 20 66 6F 75 6E 64 20 74 68 61 74 20 37 2B 31 20 7/31 or 7, it is found that 7+1 0000BAA0 69 73 20 64 69 76 69 73 69 62 6C 65 20 62 79 20 38 2E 0D 0A 0D 0A 73 61 76 65 20 73 68 69 66 74 is divisible by 8.♪◙♪◙save shift 0000BAC0 20 3D 20 33 20 61 6E 64 20 6F 72 64 69 6E 61 6C 20 3D 20 73 75 62 5F 6F 70 65 72 61 6E 64 0D 0A = 3 and ordinal = sub_operand♪◙ 0000BAE0 0D 0A 41 66 74 65 72 20 66 61 63 74 6F 72 69 6E 67 2C 20 74 68 65 20 69 6E 73 74 72 75 63 74 69 ♪◙After factoring, the instructi 0000BB00 6F 6E 73 20 63 61 6E 20 62 65 20 67 65 6E 65 72 61 74 65 64 20 69 6E 20 72 65 76 65 72 73 65 2E ons can be generated in reverse. 0000BB20 0D 0A 0D 0A 20 20 20 20 20 20 20 20 20 20 20 20 20 20 6D 6F 76 20 20 65 63 78 2C 20 65 61 78 20 ♪◙♪◙ mov ecx, eax 0000BB40 20 20 20 20 20 20 3B 20 31 0D 0A 20 20 20 20 20 20 20 73 68 6C 20 20 65 61 78 2C 20 33 20 20 20 ; 1♪◙ shl eax, 3 0000BB60 20 20 20 20 20 20 3B 20 32 20 20 20 20 20 20 20 20 20 20 20 0D 0A 20 20 20 20 20 20 20 73 75 62 ; 2 ♪◙ sub 0000BB80 20 20 65 61 78 2C 20 65 63 78 20 20 20 20 20 20 20 3B 20 33 0D 0A 20 20 20 20 20 20 20 6D 6F 76 eax, ecx ; 3♪◙ mov 0000BBA0 20 20 65 63 78 2C 20 65 61 78 20 20 20 20 20 20 20 3B 20 34 0D 0A 20 20 20 20 20 20 20 73 68 6C ecx, eax ; 4♪◙ shl 0000BBC0 20 20 65 61 78 2C 20 35 20 20 20 20 20 20 20 20 20 3B 20 35 0D 0A 20 20 20 20 20 20 20 73 75 62 eax, 5 ; 5♪◙ sub 0000BBE0 20 20 65 61 78 2C 20 65 63 78 20 20 20 20 20 20 20 3B 20 36 20 20 20 20 20 20 20 20 20 20 20 20 eax, ecx ; 6 0000BC00 20 20 20 20 20 20 20 20 0D 0A 0D 0A 54 68 69 73 20 63 6F 64 65 20 73 65 71 75 65 6E 63 65 20 61 ♪◙♪◙This code sequence a 0000BC20 6C 6C 6F 77 73 20 73 63 68 65 64 75 6C 69 6E 67 20 6F 66 20 6F 74 68 65 72 20 69 6E 73 74 72 75 llows scheduling of other instru 0000BC40 63 74 69 6F 6E 73 20 69 6E 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 27 ctions in the Pentium processor' 0000BC60 73 20 56 20 20 70 69 70 65 2E 0D 0A 0D 0A 36 2E 20 50 72 6F 63 65 73 73 6F 72 20 53 70 65 63 69 s V pipe.♪◙♪◙6. Processor Speci 0000BC80 66 69 63 20 4F 70 74 69 6D 69 7A 61 74 69 6F 6E 73 0D 0A 0D 0A 36 2E 31 20 50 65 6E 74 69 75 6D fic Optimizations♪◙♪◙6.1 Pentium 0000BCA0 20 50 72 6F 63 65 73 73 6F 72 20 46 6C 6F 61 74 69 6E 67 2D 50 6F 69 6E 74 20 4F 70 74 69 6D 69 Processor Floating-Point Optimi 0000BCC0 7A 61 74 69 6F 6E 73 0D 0A 0D 0A 54 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 zations♪◙♪◙The Pentium processor 0000BCE0 20 69 73 20 74 68 65 20 66 69 72 73 74 20 67 65 6E 65 72 61 74 69 6F 6E 20 6F 66 20 74 68 65 20 is the first generation of the 0000BD00 49 6E 74 65 6C 33 38 36 20 66 61 6D 69 6C 79 20 74 68 61 74 20 69 6D 70 6C 65 6D 65 6E 74 73 20 Intel386 family that implements 0000BD20 61 20 70 69 70 65 6C 69 6E 65 64 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 75 6E 69 74 2E a pipelined floating-point unit. 0000BD40 20 20 48 6F 77 65 76 65 72 2C 20 69 6E 20 6F 72 64 65 72 20 74 6F 20 61 63 68 69 65 76 65 20 6D However, in order to achieve m 0000BD60 61 78 69 6D 75 6D 20 74 68 72 6F 75 67 68 70 75 74 20 66 72 6F 6D 20 74 68 65 20 50 65 6E 74 69 aximum throughput from the Penti 0000BD80 75 6D 20 70 72 6F 63 65 73 73 6F 72 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 75 6E 69 74 um processor floating-point unit 0000BDA0 2C 20 73 70 65 63 69 66 69 63 20 6F 70 74 69 6D 69 7A 61 74 69 6F 6E 73 20 6D 75 73 74 20 62 65 , specific optimizations must be 0000BDC0 20 64 6F 6E 65 2E 0D 0A 0D 0A 36 2E 31 2E 31 20 46 6C 6F 61 74 69 6E 67 2D 50 6F 69 6E 74 20 45 done.♪◙♪◙6.1.1 Floating-Point E 0000BDE0 78 61 6D 70 6C 65 0D 0A 0D 0A 46 4F 52 54 52 41 4E 20 73 6F 75 72 63 65 3A 0D 0A 0D 0A 09 73 75 xample♪◙♪◙FORTRAN source:♪◙♪◙○su 0000BE00 62 72 6F 75 74 69 6E 65 20 64 61 28 78 2C 79 2C 7A 2C 6E 29 0D 0A 09 64 69 6D 65 6E 73 69 6F 6E broutine da(x,y,z,n)♪◙○dimension 0000BE20 20 78 28 6E 29 2C 79 28 6E 29 0D 0A 0D 0A 09 64 6F 20 31 30 20 69 3D 6C 2C 6E 0D 0A 31 30 20 20 x(n),y(n)♪◙♪◙○do 10 i=l,n♪◙10 0000BE40 20 09 20 78 28 69 29 20 3D 20 78 28 69 29 20 2B 20 79 28 69 29 20 2A 20 7A 0D 0A 0D 0A 09 72 65 ○ x(i) = x(i) + y(i) * z♪◙♪◙○re 0000BE60 74 75 72 6E 0D 0A 09 65 6E 64 0D 0A 0D 0A 0D 0A 41 73 73 65 6D 62 6C 79 20 63 6F 64 65 3A 20 20 turn♪◙○end♪◙♪◙♪◙Assembly code: 0000BE80 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 0D 0A 0D 0A 20 20 ♪◙♪◙ 0000BEA0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 0000BEC0 20 20 20 20 50 65 6E 74 69 75 6D 2F 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 0D 0A Pentium/Intel486 processor♪◙ 0000BEE0 20 20 20 20 54 6F 70 4F 66 4C 6F 6F 70 3A 0D 0A 20 20 20 20 20 20 20 20 66 6C 64 20 20 20 64 77 TopOfLoop:♪◙ fld dw 0000BF00 6F 72 64 20 70 74 72 20 5B 65 73 70 2B 38 5D 20 09 09 3B 20 31 20 20 20 20 2F 20 20 20 20 31 0D ord ptr [esp+8] ○○; 1 / 1♪ 0000BF20 0A 20 20 20 20 20 20 20 20 66 6D 75 6C 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 62 78 2B 65 61 ◙ fmul dword ptr [ebx+ea 0000BF40 78 2A 34 5D 20 09 3B 20 32 20 20 20 20 2F 20 20 20 20 35 0D 0A 20 20 20 20 20 20 20 20 66 61 64 x*4] ○; 2 / 5♪◙ fad 0000BF60 64 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 63 78 2B 65 61 78 2A 34 5D 20 09 3B 20 35 20 20 20 d dword ptr [ecx+eax*4] ○; 5 0000BF80 20 2F 20 20 20 31 36 0D 0A 20 20 20 20 20 20 20 20 66 73 74 70 20 20 64 77 6F 72 64 20 70 74 72 / 16♪◙ fstp dword ptr 0000BFA0 20 5B 65 63 78 2B 65 61 78 2A 34 5D 09 09 3B 20 39 20 20 20 20 2F 20 20 20 32 36 0D 0A 20 20 20 [ecx+eax*4]○○; 9 / 26♪◙ 0000BFC0 20 20 20 20 20 69 6E 63 20 20 20 65 61 78 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 inc eax 0000BFE0 20 20 20 09 3B 20 31 31 20 20 20 2F 20 20 20 33 33 0D 0A 20 20 20 20 20 20 20 20 63 6D 70 20 20 ○; 11 / 33♪◙ cmp 0000C000 20 65 61 78 2C 20 65 62 70 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 09 3B 20 31 32 20 20 eax, ebp ○; 12 0000C020 20 2F 20 20 20 33 34 0D 0A 20 20 20 20 20 20 20 20 6A 6C 65 20 20 20 20 20 20 54 6F 70 4F 66 4C / 34♪◙ jle TopOfL 0000C040 6F 6F 70 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 09 3B 20 31 32 20 20 20 2F 20 20 20 33 36 oop ○; 12 / 36 0000C060 2B 32 20 66 6F 72 20 62 72 61 6E 63 68 0D 0A 0D 0A 54 6F 74 61 6C 20 3A 31 32 20 63 79 63 6C 65 +2 for branch♪◙♪◙Total :12 cycle 0000C080 73 20 70 65 72 20 69 74 65 72 61 74 69 6F 6E 0D 0A 0D 0A 4F 6E 20 74 68 65 20 49 6E 74 65 6C 34 s per iteration♪◙♪◙On the Intel4 0000C0A0 38 36 20 70 72 6F 63 65 73 73 6F 72 2C 20 74 68 65 20 74 69 6D 65 20 69 74 20 74 61 6B 65 73 20 86 processor, the time it takes 0000C0C0 74 6F 20 61 64 64 20 61 6E 64 20 6D 75 6C 74 69 70 6C 79 20 76 61 72 69 65 73 20 64 65 70 65 6E to add and multiply varies depen 0000C0E0 64 69 6E 67 20 6F 6E 20 74 68 65 20 76 61 6C 75 65 73 2E 20 49 6E 20 74 68 69 73 20 65 78 61 6D ding on the values. In this exam 0000C100 70 6C 65 2C 20 31 31 20 77 61 73 20 75 73 65 64 20 66 6F 72 20 6D 75 6C 74 69 70 6C 79 20 61 6E ple, 11 was used for multiply an 0000C120 64 20 31 30 20 66 6F 72 20 61 64 64 2E 20 54 68 65 20 6C 6F 61 64 20 74 61 6B 65 73 20 33 20 63 d 10 for add. The load takes 3 c 0000C140 6C 6F 63 6B 73 3B 20 74 68 65 20 73 74 6F 72 65 20 72 65 71 75 69 72 65 73 20 37 20 63 6C 6F 63 locks; the store requires 7 cloc 0000C160 6B 73 2E 20 54 68 65 20 65 78 74 72 61 20 63 79 63 6C 65 20 62 65 66 6F 72 65 20 74 68 65 20 66 ks. The extra cycle before the f 0000C180 6D 75 6C 20 69 73 20 61 6E 20 69 6E 64 65 78 20 70 65 6E 61 6C 74 79 20 66 6F 72 20 74 68 65 20 mul is an index penalty for the 0000C1A0 66 6D 75 6C 2E 20 54 68 65 20 66 61 64 64 20 61 6E 64 20 66 73 74 70 20 64 6F 20 6E 6F 74 20 73 fmul. The fadd and fstp do not s 0000C1C0 68 6F 77 20 61 6E 20 69 6E 64 65 78 20 70 65 6E 61 6C 74 79 20 62 65 63 61 75 73 65 20 74 68 65 how an index penalty because the 0000C1E0 20 70 65 6E 61 6C 74 79 20 6F 76 65 72 6C 61 70 70 65 64 20 77 69 74 68 20 74 68 65 20 65 78 65 penalty overlapped with the exe 0000C200 63 75 74 69 6F 6E 20 6F 66 20 74 68 65 20 70 72 65 76 69 6F 75 73 20 66 6C 6F 61 74 69 6E 67 2D cution of the previous floating- 0000C220 70 6F 69 6E 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 2E 20 54 68 65 73 65 20 6F 76 65 72 6C 61 70 point instruction. These overlap 0000C240 73 20 64 6F 20 6E 6F 74 20 6F 63 63 75 72 20 77 69 74 68 20 66 6C 64 20 6F 72 20 66 78 63 68 2E s do not occur with fld or fxch. 0000C260 0D 0A 0D 0A 4F 6E 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 2C 20 74 68 ♪◙♪◙On the Pentium processor, th 0000C280 65 20 72 65 73 75 6C 74 73 20 6F 66 20 66 61 64 64 20 61 6E 64 20 66 6D 75 6C 20 63 61 6E 20 62 e results of fadd and fmul can b 0000C2A0 65 20 75 73 65 64 20 74 68 72 65 65 20 63 79 63 6C 65 73 20 61 66 74 65 72 20 74 68 65 79 20 73 e used three cycles after they s 0000C2C0 74 61 72 74 2C 20 65 78 63 65 70 74 20 77 68 65 6E 20 74 68 65 20 75 73 65 20 69 73 20 66 73 74 tart, except when the use is fst 0000C2E0 2E 20 57 68 65 6E 20 61 6E 20 66 73 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 75 73 65 73 20 74 . When an fst instruction uses t 0000C300 68 65 20 72 65 73 75 6C 74 20 6F 66 20 61 6E 6F 74 68 65 72 20 66 6C 6F 61 74 69 6E 67 2D 70 6F he result of another floating-po 0000C320 69 6E 74 20 6F 70 65 72 61 74 69 6F 6E 2C 20 61 6E 20 65 78 74 72 61 20 63 79 63 6C 65 20 69 73 int operation, an extra cycle is 0000C340 20 6E 65 65 64 65 64 2E 20 54 68 65 20 66 73 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 65 78 65 needed. The fst instruction exe 0000C360 63 75 74 65 73 20 66 6F 72 20 74 77 6F 20 63 79 63 6C 65 73 20 61 6E 64 20 6E 6F 74 68 69 6E 67 cutes for two cycles and nothing 0000C380 20 63 61 6E 20 65 78 65 63 75 74 65 20 69 6E 20 70 61 72 61 6C 6C 65 6C 2E 0D 0A 0D 0A 54 68 65 can execute in parallel.♪◙♪◙The 0000C3A0 72 65 20 69 73 20 61 6E 20 65 6E 6F 72 6D 6F 75 73 20 69 6D 70 72 6F 76 65 6D 65 6E 74 20 64 75 re is an enormous improvement du 0000C3C0 65 20 74 6F 20 64 65 63 72 65 61 73 69 6E 67 20 74 68 65 20 63 6C 6F 63 6B 20 63 6F 75 6E 74 73 e to decreasing the clock counts 0000C3E0 20 66 6F 72 20 74 68 65 20 63 6F 6D 6D 6F 6E 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 69 for the common floating-point i 0000C400 6E 73 74 72 75 63 74 69 6F 6E 73 3B 20 68 6F 77 65 76 65 72 2C 20 74 68 69 73 20 65 78 61 6D 70 nstructions; however, this examp 0000C420 6C 65 20 64 6F 65 73 20 6E 6F 74 20 6F 76 65 72 6C 61 70 20 61 6E 79 20 66 6C 6F 61 74 69 6E 67 le does not overlap any floating 0000C440 2D 70 6F 69 6E 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 2E 20 41 20 66 75 72 74 68 65 72 20 69 -point instructions. A further i 0000C460 6D 70 72 6F 76 65 6D 65 6E 74 20 63 61 6E 20 62 65 20 61 63 68 69 65 76 65 64 20 62 79 20 6F 76 mprovement can be achieved by ov 0000C480 65 72 6C 61 70 70 69 6E 67 20 74 68 65 20 65 78 65 63 75 74 69 6F 6E 20 6F 66 20 74 68 65 20 66 erlapping the execution of the f 0000C4A0 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 61 73 20 65 78 loating-point instructions as ex 0000C4C0 70 6C 61 69 6E 65 64 20 69 6E 20 74 68 65 20 6E 65 78 74 20 73 65 63 74 69 6F 6E 2E 0D 0A 0D 0A plained in the next section.♪◙♪◙ 0000C4E0 54 6F 20 65 78 70 6F 73 65 20 6D 6F 72 65 20 70 61 72 61 6C 6C 65 6C 69 73 6D 2C 20 6C 6F 6F 70 To expose more parallelism, loop 0000C500 20 75 6E 72 6F 6C 6C 69 6E 67 20 63 61 6E 20 62 65 20 75 73 65 64 20 69 66 20 74 68 65 20 69 74 unrolling can be used if the it 0000C520 65 72 61 74 69 6F 6E 73 20 61 72 65 20 69 6E 64 65 70 65 6E 64 65 6E 74 2E 0D 0A 46 6F 6C 6C 6F erations are independent.♪◙Follo 0000C540 77 69 6E 67 20 69 73 20 74 68 65 20 61 73 73 65 6D 62 6C 79 20 63 6F 64 65 20 61 66 74 65 72 20 wing is the assembly code after 0000C560 75 6E 72 6F 6C 6C 69 6E 67 3A 0D 0A 0D 0A 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 unrolling:♪◙♪◙ 0000C580 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 Pentium proce 0000C5A0 73 73 6F 72 20 20 20 20 20 49 6E 74 65 6C 34 38 36 20 43 50 55 0D 0A 20 20 20 54 6F 70 4F 66 4C ssor Intel486 CPU♪◙ TopOfL 0000C5C0 6F 6F 70 3A 0D 0A 20 20 20 20 20 20 20 20 66 6C 64 20 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 oop:♪◙ fld dword ptr [e 0000C5E0 73 70 2B 38 5D 20 09 3B 20 20 31 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 31 0D sp+8] ○; 1 1♪ 0000C600 0A 20 20 20 20 20 20 20 20 66 6D 75 6C 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 62 78 2B 65 61 ◙ fmul dword ptr [ebx+ea 0000C620 78 2A 34 5D 09 3B 20 20 32 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 35 0D 0A 20 x*4]○; 2 5♪◙ 0000C640 20 20 20 20 20 20 20 66 61 64 64 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 63 78 2B 65 61 78 2A fadd dword ptr [ecx+eax* 0000C660 34 5D 09 3B 20 20 35 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 31 36 0D 0A 20 20 20 4]○; 5 16♪◙ 0000C680 20 20 20 20 20 66 73 74 70 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 63 78 2B 65 61 78 2A 34 5D fstp dword ptr [ecx+eax*4] 0000C6A0 20 09 3B 20 20 39 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 32 36 0D 0A 20 20 20 20 ○; 9 26♪◙ 0000C6C0 20 20 20 20 66 6C 64 20 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 73 70 2B 38 5D 09 3B 20 20 31 fld dword ptr [esp+8]○; 1 0000C6E0 31 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 33 33 0D 0A 20 20 20 20 20 20 20 20 66 6D 1 33♪◙ fm 0000C700 75 6C 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 62 78 2B 65 61 78 2A 34 2B 34 5D 09 3B 20 20 31 ul dword ptr [ebx+eax*4+4]○; 1 0000C720 32 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 33 37 0D 0A 20 20 20 20 20 20 20 20 66 61 2 37♪◙ fa 0000C740 64 64 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 63 78 2B 65 61 78 2A 34 2B 34 5D 09 3B 20 20 31 dd dword ptr [ecx+eax*4+4]○; 1 0000C760 35 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 34 38 0D 0A 20 20 20 20 20 20 20 20 66 73 5 48♪◙ fs 0000C780 74 70 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 63 78 2B 65 61 78 2A 34 2B 34 5D 09 3B 20 20 31 tp dword ptr [ecx+eax*4+4]○; 1 0000C7A0 39 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 35 38 0D 0A 20 20 20 20 20 20 20 20 66 6C 9 58♪◙ fl 0000C7C0 64 20 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 73 70 2B 38 5D 09 3B 20 20 32 31 20 20 20 20 20 d dword ptr [esp+8]○; 21 0000C7E0 20 20 20 20 20 20 20 20 20 20 20 20 36 35 0D 0A 20 20 20 20 20 20 20 20 66 6D 75 6C 20 20 64 77 65♪◙ fmul dw 0000C800 6F 72 64 20 70 74 72 20 5B 65 62 78 2B 65 61 78 2A 34 2B 38 5D 09 3B 20 20 32 32 20 20 20 20 20 ord ptr [ebx+eax*4+8]○; 22 0000C820 20 20 20 20 20 20 20 20 20 20 20 20 36 39 0D 0A 20 20 20 20 20 20 20 20 66 61 64 64 20 20 64 77 69♪◙ fadd dw 0000C840 6F 72 64 20 70 74 72 20 5B 65 63 78 2B 65 61 78 2A 34 2B 38 5D 09 3B 20 20 32 35 20 20 20 20 20 ord ptr [ecx+eax*4+8]○; 25 0000C860 20 20 20 20 20 20 20 20 20 20 20 20 38 30 0D 0A 20 20 20 20 20 20 20 20 66 73 74 70 20 20 64 77 80♪◙ fstp dw 0000C880 6F 72 64 20 70 74 72 20 5B 65 63 78 2B 65 61 78 2A 34 2B 38 5D 09 3B 20 20 32 39 20 20 20 20 20 ord ptr [ecx+eax*4+8]○; 29 0000C8A0 20 20 20 20 20 20 20 20 20 20 20 20 39 30 0D 0A 20 20 20 20 20 20 20 20 61 64 64 20 20 20 65 61 90♪◙ add ea 0000C8C0 78 2C 20 33 09 3B 20 20 33 31 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 39 37 0D 0A 20 x, 3○; 31 97♪◙ 0000C8E0 20 20 20 20 20 20 20 63 6D 70 20 20 20 65 61 78 2C 20 65 62 70 09 3B 20 20 33 32 20 20 20 20 20 cmp eax, ebp○; 32 0000C900 20 20 20 20 20 20 20 20 20 20 20 20 39 38 0D 0A 20 20 20 20 20 20 20 20 6A 6C 65 20 20 20 54 6F 98♪◙ jle To 0000C920 70 4F 66 4C 6F 6F 70 09 3B 20 20 33 32 20 20 20 20 20 20 20 20 20 20 20 20 31 30 30 2B 32 20 28 pOfLoop○; 32 100+2 ( 0000C940 62 72 20 74 61 6B 65 6E 29 0D 0A 0D 0A 54 6F 74 61 6C 3A 20 33 32 20 63 79 63 6C 65 73 20 28 31 br taken)♪◙♪◙Total: 32 cycles (1 0000C960 30 2E 37 2F 20 69 74 65 72 61 74 69 6F 6E 29 0D 0A 0D 0A 54 68 65 20 63 6C 6F 63 6B 20 63 6F 75 0.7/ iteration)♪◙♪◙The clock cou 0000C980 6E 74 20 69 6D 70 72 6F 76 65 6D 65 6E 74 73 20 67 61 69 6E 65 64 20 74 68 72 6F 75 67 68 20 6C nt improvements gained through l 0000C9A0 6F 6F 70 20 75 6E 72 6F 6C 6C 69 6E 67 20 77 61 73 20 64 75 65 20 74 6F 20 65 6C 69 6D 69 6E 61 oop unrolling was due to elimina 0000C9C0 74 69 6E 67 20 73 6F 6D 65 20 6F 66 20 74 68 65 20 6C 6F 6F 70 20 63 6F 6E 74 72 6F 6C 20 6F 76 ting some of the loop control ov 0000C9E0 65 72 68 65 61 64 2E 20 20 54 6F 20 67 65 74 20 6D 6F 72 65 20 69 6D 70 72 6F 76 65 6D 65 6E 74 erhead. To get more improvement 0000CA00 2C 20 77 65 20 6E 65 65 64 20 74 6F 20 67 65 74 20 74 68 65 20 66 6C 6F 61 74 69 6E 67 2D 70 6F , we need to get the floating-po 0000CA20 69 6E 74 20 6F 70 65 72 61 74 69 6F 6E 73 20 6F 76 65 72 6C 61 70 70 65 64 20 69 6E 20 6F 72 64 int operations overlapped in ord 0000CA40 65 72 20 74 6F 20 68 69 64 65 20 74 68 65 69 72 20 6C 61 74 65 6E 63 69 65 73 2E 0D 0A 0D 0A 4D er to hide their latencies.♪◙♪◙M 0000CA60 6F 73 74 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 6F 70 65 72 61 74 69 6F 6E 73 20 72 65 ost floating-point operations re 0000CA80 71 75 69 72 65 20 74 68 61 74 20 6F 6E 65 20 6F 70 65 72 61 6E 64 20 61 6E 64 20 74 68 65 20 72 quire that one operand and the r 0000CAA0 65 73 75 6C 74 20 75 73 65 20 74 68 65 20 74 6F 70 20 6F 66 20 73 74 61 63 6B 2E 20 54 68 69 73 esult use the top of stack. This 0000CAC0 20 6D 61 6B 65 73 20 65 61 63 68 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 64 65 70 65 6E 64 65 6E makes each instruction dependen 0000CAE0 74 20 6F 6E 20 74 68 65 20 70 72 65 76 69 6F 75 73 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 61 6E t on the previous instruction an 0000CB00 64 20 69 6E 68 69 62 69 74 73 20 6F 76 65 72 6C 61 70 70 69 6E 67 20 74 68 65 20 69 6E 73 74 72 d inhibits overlapping the instr 0000CB20 75 63 74 69 6F 6E 73 20 2E 0D 0A 0D 0A 4F 6E 65 20 6F 62 76 69 6F 75 73 20 77 61 79 20 74 6F 20 uctions .♪◙♪◙One obvious way to 0000CB40 67 65 74 20 61 72 6F 75 6E 64 20 74 68 69 73 20 69 73 20 74 6F 20 63 68 61 6E 67 65 20 74 68 65 get around this is to change the 0000CB60 20 61 72 63 68 69 74 65 63 74 75 72 65 20 61 6E 64 20 68 61 76 65 20 66 6C 6F 61 74 69 6E 67 2D architecture and have floating- 0000CB80 70 6F 69 6E 74 20 72 65 67 69 73 74 65 72 73 2C 20 72 61 74 68 65 72 20 74 68 61 6E 20 61 20 73 point registers, rather than a s 0000CBA0 74 61 63 6B 2E 20 55 6E 66 6F 72 74 75 6E 61 74 65 6C 79 2C 20 75 70 77 61 72 64 20 61 6E 64 20 tack. Unfortunately, upward and 0000CBC0 64 6F 77 6E 77 61 72 64 20 63 6F 6D 70 61 74 69 62 69 6C 69 74 79 20 77 6F 75 6C 64 20 62 65 20 downward compatibility would be 0000CBE0 6C 6F 73 74 2E 20 20 20 49 6E 73 74 65 61 64 2C 20 74 68 65 20 66 78 63 68 20 69 6E 73 74 72 75 lost. Instead, the fxch instru 0000CC00 63 74 69 6F 6E 20 77 61 73 20 6D 61 64 65 20 22 66 61 73 74 22 2E 20 54 68 69 73 20 70 72 6F 76 ction was made "fast". This prov 0000CC20 69 64 65 73 20 75 73 20 61 6E 6F 74 68 65 72 20 77 61 79 20 74 6F 20 61 76 6F 69 64 20 74 68 65 ides us another way to avoid the 0000CC40 20 74 6F 70 20 6F 66 20 73 74 61 63 6B 20 64 65 70 65 6E 64 65 6E 63 69 65 73 2E 20 20 54 68 65 top of stack dependencies. The 0000CC60 20 66 78 63 68 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 63 61 6E 20 62 65 20 70 61 69 72 65 64 fxch instructions can be paired 0000CC80 20 77 69 74 68 20 74 68 65 20 63 6F 6D 6D 6F 6E 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 with the common floating-point 0000CCA0 6F 70 65 72 61 74 69 6F 6E 73 2C 20 73 6F 20 74 68 65 72 65 20 69 73 20 6E 6F 20 70 65 6E 61 6C operations, so there is no penal 0000CCC0 74 79 20 6F 6E 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 2E 20 20 4F 6E ty on the Pentium processor. On 0000CCE0 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 2C 20 65 61 63 68 20 66 78 the Intel486 processor, each fx 0000CD00 63 68 20 74 61 6B 65 73 20 34 20 63 6C 6F 63 6B 73 2E 0D 0A 0D 0A 54 6F 20 74 61 6B 65 20 61 64 ch takes 4 clocks.♪◙♪◙To take ad 0000CD20 76 61 6E 74 61 67 65 20 6F 66 20 74 68 65 20 65 78 70 6F 73 65 64 20 70 61 72 61 6C 6C 65 6C 69 vantage of the exposed paralleli 0000CD40 73 6D 20 66 72 6F 6D 20 6C 6F 6F 70 20 75 6E 72 6F 6C 6C 69 6E 67 2C 20 74 68 65 20 69 6E 73 74 sm from loop unrolling, the inst 0000CD60 72 75 63 74 69 6F 6E 73 20 73 68 6F 75 6C 64 20 62 65 20 73 63 68 65 64 75 6C 65 64 2E 0D 0A 0D ructions should be scheduled.♪◙♪ 0000CD80 0A 0C 41 73 73 65 6D 62 6C 79 20 63 6F 64 65 20 61 66 74 65 72 20 75 6E 72 6F 6C 6C 69 6E 67 20 ◙♀Assembly code after unrolling 0000CDA0 61 6E 64 20 73 63 68 65 64 75 6C 69 6E 67 3A 0D 0A 0D 0A 20 20 20 20 20 20 20 20 20 20 20 20 20 and scheduling:♪◙♪◙ 0000CDC0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 0000CDE0 20 20 20 20 20 20 20 20 20 20 20 41 66 74 65 72 20 49 6E 73 74 72 75 63 74 69 6F 6E 0D 0A 20 20 After Instruction♪◙ 0000CE00 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 0000CE20 20 20 49 6E 74 65 6C 34 38 36 20 20 50 65 6E 74 69 75 6D 20 20 20 53 54 28 4F 29 20 20 20 20 20 Intel486 Pentium ST(O) 0000CE40 53 54 28 6C 29 20 20 20 20 53 54 28 32 29 0D 0A 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ST(l) ST(2)♪◙ 0000CE60 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 43 50 55 20 20 20 20 20 20 CPU 0000CE80 43 50 55 20 20 20 20 20 2D 2D 2D 2D 2D 2D 2D 2D 20 20 2D 2D 2D 2D 2D 2D 2D 2D 20 2D 2D 2D 2D 2D CPU -------- -------- ----- 0000CEA0 0D 0A 54 6F 70 4F 66 4C 6F 6F 70 3A 20 0D 0A 20 20 20 20 66 6C 64 20 20 20 20 20 20 20 64 77 6F ♪◙TopOfLoop: ♪◙ fld dwo 0000CEC0 72 64 20 70 74 72 20 5B 65 73 70 2B 38 5D 20 20 20 20 20 20 20 20 20 20 31 20 20 20 20 20 20 20 rd ptr [esp+8] 1 0000CEE0 31 20 20 20 20 20 20 7A 0D 0A 20 20 20 20 66 6D 75 6C 20 20 20 20 20 20 64 77 6F 72 64 20 70 74 1 z♪◙ fmul dword pt 0000CF00 72 20 5B 65 62 78 2B 65 61 78 2A 34 5D 20 20 20 20 20 20 35 20 20 20 20 20 20 20 32 20 20 20 20 r [ebx+eax*4] 5 2 0000CF20 20 20 79 30 2A 7A 0D 0A 20 20 20 20 66 6C 64 20 20 20 20 20 20 20 64 77 6F 72 64 20 70 74 72 20 y0*z♪◙ fld dword ptr 0000CF40 5B 65 73 70 2B 38 5D 20 20 20 20 20 20 20 20 20 31 36 20 20 20 20 20 20 20 33 20 20 20 20 20 20 [esp+8] 16 3 0000CF60 7A 20 20 20 20 20 20 20 20 20 79 30 2A 7A 0D 0A 20 20 20 20 66 6D 75 6C 20 20 20 20 20 20 64 77 z y0*z♪◙ fmul dw 0000CF80 6F 72 64 20 70 74 72 20 5B 65 62 78 2B 65 61 78 2A 34 2B 34 5D 20 20 20 32 30 20 20 20 20 20 20 ord ptr [ebx+eax*4+4] 20 0000CFA0 20 34 20 20 20 20 20 20 79 6C 2A 7A 20 20 20 20 20 20 79 30 2A 7A 0D 0A 20 20 20 20 66 78 63 68 4 yl*z y0*z♪◙ fxch 0000CFC0 20 20 20 20 20 20 73 74 28 6C 29 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 st(l) 0000CFE0 33 31 20 20 20 20 20 20 20 34 20 20 20 20 20 20 79 30 2A 7A 20 20 20 20 20 20 79 6C 2A 7A 0D 0A 31 4 y0*z yl*z♪◙ 0000D000 20 20 20 20 66 61 64 64 20 20 20 20 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 63 78 2B 65 61 78 fadd dword ptr [ecx+eax 0000D020 2A 34 5D 20 20 20 20 20 33 36 20 20 20 20 20 20 20 35 20 20 20 20 20 20 78 30 2B 79 30 2A 7A 20 *4] 36 5 x0+y0*z 0000D040 20 20 79 6C 2A 7A 0D 0A 20 20 20 20 66 6C 64 20 20 20 20 20 20 20 64 77 6F 72 64 20 70 74 72 20 yl*z♪◙ fld dword ptr 0000D060 5B 65 73 70 2B 38 5D 20 20 20 20 20 20 20 20 20 34 36 20 20 20 20 20 20 20 36 20 20 20 20 20 20 [esp+8] 46 6 0000D080 7A 20 20 20 20 20 20 20 20 20 78 30 2B 79 30 2A 7A 20 20 20 79 6C 2A 7A 0D 0A 20 20 20 20 66 6D z x0+y0*z yl*z♪◙ fm 0000D0A0 75 6C 20 20 20 20 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 62 78 2B 65 61 78 2A 34 2B 38 5D 20 ul dword ptr [ebx+eax*4+8] 0000D0C0 20 20 35 30 20 20 20 20 20 20 20 37 20 20 20 20 20 20 79 32 2A 7A 20 20 20 20 20 20 78 30 2B 79 50 7 y2*z x0+y 0000D0E0 30 2A 7A 20 20 20 79 6C 2A 7A 0D 0A 20 20 20 20 66 78 63 68 20 20 20 20 20 20 73 74 28 32 29 20 0*z yl*z♪◙ fxch st(2) 0000D100 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 36 31 20 20 20 20 20 20 20 37 20 20 61 7 0000D120 20 20 20 20 79 6C 2A 7A 20 20 20 20 20 20 78 30 2B 79 30 2A 7A 20 20 20 79 32 2A 7A 0D 0A 20 20 yl*z x0+y0*z y2*z♪◙ 0000D140 20 20 66 61 64 64 20 20 20 20 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 63 78 2B 65 61 78 2A 34 fadd dword ptr [ecx+eax*4 0000D160 2B 34 5D 20 20 20 36 36 20 20 20 20 20 20 20 38 20 20 20 20 20 20 78 6C 2B 79 6C 2A 7A 20 20 20 +4] 66 8 xl+yl*z 0000D180 78 30 2B 79 30 2A 7A 20 20 20 79 32 2A 7A 0D 0A 20 20 20 20 66 78 63 68 20 20 20 20 20 20 73 74 x0+y0*z y2*z♪◙ fxch st 0000D1A0 28 6C 29 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 37 36 20 20 20 20 20 20 (l) 76 0000D1C0 20 38 20 20 20 20 20 20 78 30 2B 79 30 2A 7A 20 20 20 78 6C 2B 79 6C 2A 7A 20 20 20 79 32 2A 7A 8 x0+y0*z xl+yl*z y2*z 0000D1E0 0D 0A 20 20 20 20 66 73 74 70 20 20 20 20 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 63 78 2B 65 ♪◙ fstp dword ptr [ecx+e 0000D200 61 78 2A 34 5D 20 20 20 20 20 38 31 20 20 20 20 20 20 20 39 20 20 20 20 20 20 78 6C 2B 79 6C 2A ax*4] 81 9 xl+yl* 0000D220 7A 20 20 20 79 32 2A 7A 0D 0A 20 20 20 20 66 78 63 68 20 20 20 20 20 20 73 74 28 6C 29 20 20 20 z y2*z♪◙ fxch st(l) 0000D240 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 38 38 20 20 20 20 20 20 31 31 20 20 20 20 88 11 0000D260 20 20 79 32 2A 7A 20 20 20 20 20 20 78 6C 2B 79 6C 2A 7A 0D 0A 20 20 20 20 66 61 64 64 20 20 20 y2*z xl+yl*z♪◙ fadd 0000D280 20 20 20 64 77 6F 72 64 20 70 74 72 20 5B 65 63 78 2B 65 61 78 2A 34 2B 38 5D 20 20 20 39 33 20 dword ptr [ecx+eax*4+8] 93 0000D2A0 20 20 20 20 20 31 32 20 20 20 20 20 20 78 32 2B 79 32 2A 7A 20 20 20 78 6C 2B 79 6C 2A 7A 0D 0A 12 x2+y2*z xl+yl*z♪◙ 0000D2C0 20 20 20 20 66 78 63 68 20 20 20 20 20 20 73 74 28 6C 29 20 20 20 20 20 20 20 20 20 20 20 20 20 fxch st(l) 0000D2E0 20 20 20 20 20 20 20 31 30 33 20 20 20 20 20 20 31 32 20 20 20 20 20 20 78 6C 2B 79 6C 2A 7A 20 103 12 xl+yl*z 0000D300 20 20 78 32 2B 79 32 2A 7A 0D 0A 20 20 20 20 66 73 74 70 20 20 20 20 20 20 64 77 6F 72 64 20 70 x2+y2*z♪◙ fstp dword p 0000D320 74 72 20 5B 65 63 78 2B 65 61 78 2A 34 2B 34 5D 20 20 31 30 38 20 20 20 20 20 20 31 33 20 20 20 tr [ecx+eax*4+4] 108 13 0000D340 20 20 20 78 32 2B 79 32 2A 7A 0D 0A 20 20 20 20 66 73 74 70 20 20 20 20 20 20 64 77 6F 72 64 20 x2+y2*z♪◙ fstp dword 0000D360 70 74 72 20 5B 65 63 78 2B 65 61 78 2A 34 2B 38 5D 20 20 31 31 36 20 20 20 20 20 20 31 36 0D 0A ptr [ecx+eax*4+8] 116 16♪◙ 0000D380 20 20 20 20 61 64 64 20 20 20 20 20 20 20 65 61 78 2C 20 33 20 20 20 20 20 20 20 20 20 20 20 20 add eax, 3 0000D3A0 20 20 20 20 20 20 20 31 32 33 20 20 20 20 20 20 31 38 0D 0A 20 20 20 20 63 6D 70 20 20 20 20 20 123 18♪◙ cmp 0000D3C0 20 20 65 61 78 2C 20 65 62 70 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 31 32 34 20 20 eax, ebp 124 0000D3E0 20 20 20 20 31 39 0D 0A 20 20 20 20 6A 6C 65 20 20 20 20 20 20 20 54 6F 70 4F 66 4C 6F 6F 70 20 19♪◙ jle TopOfLoop 0000D400 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 31 32 36 2B 32 20 20 20 20 31 39 0D 0A 0D 0A 20 20 126+2 19♪◙♪◙ 0000D420 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 0000D440 20 20 20 20 20 20 20 20 20 7C 0D 0A 0D 0A 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 |♪◙♪◙ 0000D460 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 28 6A 6C 65 20 74 61 6B 65 6E 29 (jle taken) 0000D480 0D 0A 0D 0A 54 6F 74 61 6C 20 3A 31 20 39 20 63 79 63 6C 65 73 20 28 36 2E 33 2F 69 74 65 72 61 ♪◙♪◙Total :1 9 cycles (6.3/itera 0000D4A0 74 69 6F 6E 29 0D 0A 0D 0A 4F 6E 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 tion)♪◙♪◙On the Intel486 process 0000D4C0 6F 72 2C 20 74 68 65 20 69 6E 64 65 78 20 70 65 6E 61 6C 74 79 20 61 6E 64 20 74 68 65 20 61 64 or, the index penalty and the ad 0000D4E0 64 65 64 20 63 6F 73 74 20 6F 66 20 66 78 63 68 20 61 72 65 20 61 70 70 61 72 65 6E 74 2E 20 54 ded cost of fxch are apparent. T 0000D500 68 65 20 69 6E 64 65 78 20 70 65 6E 61 6C 74 79 20 64 6F 65 73 20 6E 6F 74 20 6F 76 65 72 6C 61 he index penalty does not overla 0000D520 70 20 77 69 74 68 20 74 68 65 20 66 78 63 68 20 69 6E 73 74 72 75 63 74 69 6F 6E 2E 0D 0A 0D 0A p with the fxch instruction.♪◙♪◙ 0000D540 4F 6E 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 2C 20 74 68 65 20 66 78 On the Pentium processor, the fx 0000D560 63 68 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 70 61 69 72 20 77 69 74 68 20 70 72 65 63 65 64 ch instructions pair with preced 0000D580 69 6E 67 20 66 61 64 64 20 61 6E 64 20 66 6D 75 6C 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 61 ing fadd and fmul instructions a 0000D5A0 6E 64 20 65 78 65 63 75 74 65 20 69 6E 20 70 61 72 61 6C 6C 65 6C 20 77 69 74 68 20 74 68 65 6D nd execute in parallel with them 0000D5C0 20 28 63 79 63 6C 65 73 20 37 2C 38 2C 31 32 29 2E 20 54 68 65 20 66 78 63 68 20 69 6E 73 74 72 (cycles 7,8,12). The fxch instr 0000D5E0 75 63 74 69 6F 6E 73 20 6D 6F 76 65 20 61 6E 20 6F 70 65 72 61 6E 64 20 69 6E 74 6F 20 70 6F 73 uctions move an operand into pos 0000D600 69 74 69 6F 6E 20 66 6F 72 20 74 68 65 20 6E 65 78 74 20 66 6C 6F 61 74 69 6E 67 20 70 6F 69 6E ition for the next floating poin 0000D620 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 2E 20 54 68 65 72 65 20 69 73 20 61 20 63 79 63 6C 65 20 t instruction. There is a cycle 0000D640 6C 6F 73 74 20 61 74 20 63 6C 6F 63 6B 20 31 35 20 64 75 65 20 74 6F 20 74 68 65 20 73 74 6F 72 lost at clock 15 due to the stor 0000D660 65 20 77 61 69 74 69 6E 67 20 33 20 63 6C 6F 63 6B 73 20 61 66 74 65 72 20 74 68 65 20 69 6E 73 e waiting 3 clocks after the ins 0000D680 74 72 75 63 74 69 6F 6E 20 64 65 66 69 6E 69 6E 67 20 69 74 73 20 6F 70 65 72 61 6E 64 2E 20 20 truction defining its operand. 0000D6A0 54 68 65 20 66 78 63 68 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 64 6F 65 73 20 6E 6F 74 20 70 61 The fxch instruction does not pa 0000D6C0 69 72 20 77 69 74 68 20 66 73 74 20 61 6E 64 20 74 61 6B 65 73 20 6F 6E 65 20 63 6C 6F 63 6B 20 ir with fst and takes one clock 0000D6E0 61 73 20 61 20 73 65 70 61 72 61 74 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 28 63 79 63 6C 65 as a separate instruction (cycle 0000D700 73 20 39 2D 31 31 29 0D 0A 0D 0A 36 2E 31 2E 32 20 46 58 43 48 20 52 75 6C 65 73 20 61 6E 64 20 s 9-11)♪◙♪◙6.1.2 FXCH Rules and 0000D720 52 65 67 75 6C 61 74 69 6F 6E 73 0D 0A 0D 0A 54 68 65 20 66 78 63 68 20 69 6E 73 74 72 75 63 74 Regulations♪◙♪◙The fxch instruct 0000D740 69 6F 6E 20 63 61 6E 20 62 65 20 65 78 65 63 75 74 65 64 20 66 6F 72 20 22 66 72 65 65 22 20 77 ion can be executed for "free" w 0000D760 68 65 6E 20 61 6C 6C 20 6F 66 20 74 68 65 20 66 6F 6C 6C 6F 77 69 6E 67 20 63 6F 6E 64 69 74 69 hen all of the following conditi 0000D780 6F 6E 73 20 6F 63 63 75 72 3A 0D 0A 0D 0A 20 41 6E 20 46 50 20 69 6E 73 74 72 75 63 74 69 6F 6E ons occur:♪◙♪◙ An FP instruction 0000D7A0 20 66 6F 6C 6C 6F 77 73 20 74 68 65 20 66 78 63 68 20 69 6E 73 74 72 75 63 74 69 6F 6E 2E 0D 0A follows the fxch instruction.♪◙ 0000D7C0 0D 0A 41 6E 20 46 50 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 62 65 6C 6F 6E 67 69 6E 67 20 74 6F ♪◙An FP instruction belonging to 0000D7E0 20 74 68 65 20 66 6F 6C 6C 6F 77 69 6E 67 20 6C 69 73 74 20 69 6D 6D 65 64 69 61 74 65 6C 79 20 the following list immediately 0000D800 70 72 65 63 65 64 65 73 20 74 68 65 20 66 78 63 68 20 69 6E 73 74 72 75 63 74 69 6F 6E 3A 20 66 precedes the fxch instruction: f 0000D820 61 64 64 2C 20 66 73 75 62 2C 20 66 6D 75 6C 2C 20 66 6C 64 2C 20 66 63 6F 6D 2C 20 66 75 63 6F add, fsub, fmul, fld, fcom, fuco 0000D840 6D 2C 20 66 63 68 73 2C 20 66 74 73 74 2C 20 66 61 62 73 2C 20 66 64 69 76 2E 0D 0A 0D 0A 54 68 m, fchs, ftst, fabs, fdiv.♪◙♪◙Th 0000D860 69 73 20 66 78 63 68 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 68 61 73 20 61 6C 72 65 61 64 79 20 is fxch instruction has already 0000D880 62 65 65 6E 20 65 78 65 63 75 74 65 64 2E 20 54 68 69 73 20 69 73 20 62 65 63 61 75 73 65 20 74 been executed. This is because t 0000D8A0 68 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 62 6F 75 6E 64 61 72 69 65 73 20 69 6E 20 74 68 65 he instruction boundaries in the 0000D8C0 20 63 61 63 68 65 20 61 72 65 20 6D 61 72 6B 65 64 20 74 68 65 20 66 69 72 73 74 20 74 69 6D 65 cache are marked the first time 0000D8E0 20 74 68 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 69 73 20 65 78 65 63 75 74 65 64 2C 20 73 6F the instruction is executed, so 0000D900 20 70 61 69 72 69 6E 67 20 6F 6E 6C 79 20 68 61 70 70 65 6E 73 20 74 68 65 20 73 65 63 6F 6E 64 pairing only happens the second 0000D920 20 74 69 6D 65 20 74 68 69 73 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 69 73 20 65 78 65 63 75 74 time this instruction is execut 0000D940 65 64 20 66 72 6F 6D 20 74 68 65 20 63 61 63 68 65 2E 0D 0A 0D 0A 54 68 69 73 20 6D 65 61 6E 73 ed from the cache.♪◙♪◙This means 0000D960 20 74 68 61 74 20 74 68 69 73 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 69 73 20 61 6C 6D 6F 73 74 that this instruction is almost 0000D980 20 22 66 72 65 65 22 20 61 6E 64 20 63 61 6E 20 62 65 20 75 73 65 64 20 74 6F 20 61 63 63 65 73 "free" and can be used to acces 0000D9A0 73 20 65 6C 65 6D 65 6E 74 73 20 69 6E 20 74 68 65 20 64 65 65 70 65 72 20 6C 65 76 65 6C 73 20 s elements in the deeper levels 0000D9C0 6F 66 20 74 68 65 20 46 50 20 73 74 61 63 6B 20 69 6E 73 74 65 61 64 20 6F 66 20 73 74 6F 72 69 of the FP stack instead of stori 0000D9E0 6E 67 20 74 68 65 6D 20 61 6E 64 20 74 68 65 6E 20 6C 6F 61 64 69 6E 67 20 74 68 65 6D 20 61 67 ng them and then loading them ag 0000DA00 61 69 6E 2E 0D 0A 0D 0A 0C 36 2E 31 2E 33 20 4D 65 6D 6F 72 79 20 4F 70 65 72 61 6E 64 73 0D 0A ain.♪◙♪◙♀6.1.3 Memory Operands♪◙ 0000DA20 0D 0A 50 65 72 66 6F 72 6D 69 6E 67 20 61 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 6F 70 ♪◙Performing a floating-point op 0000DA40 65 72 61 74 69 6F 6E 20 6F 6E 20 61 20 6D 65 6D 6F 72 79 20 6F 70 65 72 61 6E 64 20 69 6E 73 74 eration on a memory operand inst 0000DA60 65 61 64 20 6F 66 20 6F 6E 20 61 20 73 74 61 63 6B 20 72 65 67 69 73 74 65 72 20 63 6F 73 74 73 ead of on a stack register costs 0000DA80 20 6E 6F 20 63 79 63 6C 65 73 2E 20 49 6E 20 74 68 65 20 69 6E 74 65 67 65 72 20 70 61 72 74 20 no cycles. In the integer part 0000DAA0 6F 66 20 74 68 65 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 2C 20 69 74 20 77 61 73 of the Pentium processor, it was 0000DAC0 20 62 65 74 74 65 72 20 74 6F 20 61 76 6F 69 64 20 6D 65 6D 6F 72 79 20 6F 70 65 72 61 6E 64 73 better to avoid memory operands 0000DAE0 2E 20 49 6E 20 74 68 65 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 70 61 72 74 2C 20 79 6F . In the floating-point part, yo 0000DB00 75 20 61 72 65 20 65 6E 63 6F 75 72 61 67 65 64 20 74 6F 20 75 73 65 20 6D 65 6D 6F 72 79 20 6F u are encouraged to use memory o 0000DB20 70 65 72 61 6E 64 73 2E 0D 0A 0D 0A 36 2E 31 2E 34 20 46 6C 6F 61 74 69 6E 67 2D 50 6F 69 6E 74 perands.♪◙♪◙6.1.4 Floating-Point 0000DB40 20 53 74 61 6C 6C 73 0D 0A 0D 0A 54 68 65 72 65 20 61 72 65 20 63 61 73 65 73 20 77 68 65 72 65 Stalls♪◙♪◙There are cases where 0000DB60 20 61 20 64 65 6C 61 79 20 6F 63 63 75 72 73 20 62 65 74 77 65 65 6E 20 74 77 6F 20 6F 70 65 72 a delay occurs between two oper 0000DB80 61 74 69 6F 6E 73 2E 20 49 6E 73 74 72 75 63 74 69 6F 6E 73 20 73 68 6F 75 6C 64 20 62 65 20 69 ations. Instructions should be i 0000DBA0 6E 73 65 72 74 65 64 20 62 65 74 77 65 65 6E 20 74 68 65 20 70 61 69 72 20 74 68 61 74 20 63 61 nserted between the pair that ca 0000DBC0 75 73 65 20 74 68 65 20 70 69 70 65 20 73 74 61 6C 6C 2E 20 54 68 65 73 65 20 69 6E 73 74 72 75 use the pipe stall. These instru 0000DBE0 63 74 69 6F 6E 73 20 63 6F 75 6C 64 20 62 65 20 69 6E 74 65 67 65 72 20 69 6E 73 74 72 75 63 74 ctions could be integer instruct 0000DC00 69 6F 6E 73 20 6F 72 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 69 6E 73 74 72 75 63 74 69 ions or floating-point instructi 0000DC20 6F 6E 73 20 74 68 61 74 20 77 69 6C 6C 20 6E 6F 74 20 63 61 75 73 65 20 61 20 6E 65 77 20 73 74 ons that will not cause a new st 0000DC40 61 6C 6C 20 74 68 65 6D 73 65 6C 76 65 73 2E 20 54 68 65 20 6E 75 6D 62 65 72 20 6F 66 20 69 6E all themselves. The number of in 0000DC60 73 74 72 75 63 74 69 6F 6E 73 20 74 68 61 74 20 73 68 6F 75 6C 64 20 62 65 20 69 6E 73 65 72 74 structions that should be insert 0000DC80 65 64 20 64 65 70 65 6E 64 73 20 6F 6E 20 74 68 65 20 64 65 6C 61 79 20 6C 65 6E 67 74 68 2E 0D ed depends on the delay length.♪ 0000DCA0 0A 0D 0A 4F 6E 65 20 65 78 61 6D 70 6C 65 20 6F 66 20 74 68 69 73 20 69 73 20 77 68 65 6E 20 61 ◙♪◙One example of this is when a 0000DCC0 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 64 65 70 65 floating-point instruction depe 0000DCE0 6E 64 73 20 6F 6E 20 74 68 65 20 72 65 73 75 6C 74 20 6F 66 20 74 68 65 20 69 6D 6D 65 64 69 61 nds on the result of the immedia 0000DD00 74 65 6C 79 20 70 72 65 63 65 64 69 6E 67 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 77 68 69 63 68 tely preceding instruction which 0000DD20 20 69 73 20 61 6C 73 6F 20 61 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 69 6E 73 74 72 75 is also a floating-point instru 0000DD40 63 74 69 6F 6E 2E 20 49 6E 20 74 68 69 73 20 63 61 73 65 2C 20 69 74 20 77 6F 75 6C 64 20 62 65 ction. In this case, it would be 0000DD60 20 61 64 76 61 6E 74 61 67 65 6F 75 73 20 74 6F 20 6D 6F 76 65 20 69 6E 74 65 67 65 72 20 69 6E advantageous to move integer in 0000DD80 73 74 72 75 63 74 69 6F 6E 73 20 62 65 74 77 65 65 6E 20 74 68 65 20 74 77 6F 20 66 70 20 69 6E structions between the two fp in 0000DDA0 73 74 72 75 63 74 69 6F 6E 73 2C 20 65 76 65 6E 20 69 66 20 74 68 65 20 69 6E 74 65 67 65 72 20 structions, even if the integer 0000DDC0 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 70 65 72 66 6F 72 6D 20 6C 6F 6F 70 20 63 6F 6E 74 72 6F instructions perform loop contro 0000DDE0 6C 2E 20 54 68 65 20 66 6F 6C 6C 6F 77 69 6E 67 20 65 78 61 6D 70 6C 65 20 72 65 73 74 72 75 63 l. The following example restruc 0000DE00 74 75 72 65 73 20 61 20 6C 6F 6F 70 20 69 6E 20 74 68 69 73 20 6D 61 6E 6E 65 72 3A 0D 0A 0D 0A tures a loop in this manner:♪◙♪◙ 0000DE20 66 6F 72 20 28 69 3D 30 3B 20 69 3C 53 69 7A 65 3B 20 69 2B 2B 29 0D 0A 09 61 72 72 61 79 31 20 for (i=0; i<Size; i++)♪◙○array1 0000DE40 5B 69 5D 20 2B 3D 20 61 72 72 61 79 32 20 5B 69 5D 3B 0D 0A 0D 0A 0D 0A 09 20 20 20 20 20 20 20 [i] += array2 [i];♪◙♪◙♪◙○ 0000DE60 50 65 6E 74 69 75 6D 20 50 72 6F 63 65 73 73 6F 72 20 20 09 20 20 20 49 6E 74 65 6C 34 38 36 20 Pentium Processor ○ Intel486 0000DE80 50 72 6F 63 65 73 73 6F 72 0D 0A 20 20 20 20 20 20 20 09 43 6C 6F 63 6B 73 20 20 20 20 20 20 20 Processor♪◙ ○Clocks 0000DEA0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 43 6C 6F 63 6B 73 0D 0A 54 6F 70 4F 66 4C 6F 6F 70 3A Clocks♪◙TopOfLoop: 0000DEC0 0D 0A 20 20 66 6C 64 73 20 20 20 5B 65 61 78 20 2B 20 61 72 72 61 79 32 5D 09 32 20 2D 20 41 47 ♪◙ flds [eax + array2]○2 - AG 0000DEE0 49 09 09 33 0D 0A 20 20 66 61 64 64 73 20 20 5B 65 61 78 20 2B 20 61 72 72 61 79 31 5D 09 31 09 I○○3♪◙ fadds [eax + array1]○1○ 0000DF00 09 33 0D 0A 20 20 66 73 74 70 73 20 20 5B 65 61 78 20 2B 20 61 72 72 61 79 31 5D 09 09 35 20 2D ○3♪◙ fstps [eax + array1]○○5 - 0000DF20 20 57 61 69 74 20 66 6F 72 20 66 61 64 64 73 09 31 34 20 2D 20 57 61 69 74 20 66 6F 72 20 66 61 Wait for fadds○14 - Wait for fa 0000DF40 64 64 73 0D 0A 20 20 61 64 64 20 20 20 20 65 61 78 2C 20 34 09 09 31 09 09 31 0D 0A 20 20 6A 6E dds♪◙ add eax, 4○○1○○1♪◙ jn 0000DF60 7A 20 20 20 20 54 6F 70 4F 66 4C 6F 6F 70 09 09 30 20 2D 20 50 61 69 72 73 20 77 69 74 68 20 61 z TopOfLoop○○0 - Pairs with a 0000DF80 64 64 09 33 0D 0A 20 20 09 20 20 20 20 20 20 20 20 20 20 2D 2D 2D 2D 2D 2D 20 20 20 20 20 20 20 dd○3♪◙ ○ ------ 0000DFA0 20 20 20 20 20 20 20 20 20 20 20 20 20 2D 2D 2D 2D 2D 2D 0D 0A 09 09 39 09 09 09 32 34 0D 0A 0D ------♪◙○○9○○○24♪◙♪ 0000DFC0 0A 0D 0A 0D 0A 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 50 65 ◙♪◙♪◙ Pe 0000DFE0 6E 74 69 75 6D 20 50 72 6F 63 65 73 73 6F 72 20 20 20 20 20 20 20 20 20 49 6E 74 65 6C 34 38 36 ntium Processor Intel486 0000E000 20 50 72 6F 63 65 73 73 6F 72 0D 0A 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 Processor♪◙ 0000E020 20 20 20 20 20 20 20 20 20 20 43 6C 6F 63 6B 73 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 Clocks 0000E040 20 20 20 20 20 43 6C 6F 63 6B 73 0D 0A 54 6F 70 4F 66 4C 6F 6F 70 3A 0D 0A 20 20 66 73 74 70 73 Clocks♪◙TopOfLoop:♪◙ fstps 0000E060 20 5B 65 61 78 20 2B 20 61 72 72 61 79 31 5D 09 34 20 2D 20 57 61 69 74 20 66 6F 72 20 66 61 64 [eax + array1]○4 - Wait for fad 0000E080 64 73 2C 41 47 49 09 31 30 20 2D 20 57 61 69 74 20 66 6F 72 20 66 61 64 64 73 0D 0A 4C 6F 6F 70 ds,AGI○10 - Wait for fadds♪◙Loop 0000E0A0 45 6E 74 72 79 50 6F 69 6E 74 3A 0D 0A 20 20 66 6C 64 73 20 20 5B 65 61 78 20 2B 20 61 72 72 61 EntryPoint:♪◙ flds [eax + arra 0000E0C0 79 32 5D 09 31 09 09 33 0D 0A 20 20 66 61 64 64 73 20 5B 65 61 78 20 2B 20 61 72 72 61 79 31 5D y2]○1○○3♪◙ fadds [eax + array1] 0000E0E0 09 31 09 09 33 0D 0A 20 20 61 64 64 20 65 61 78 2C 20 34 09 09 31 09 09 31 0D 0A 20 20 6A 6E 7A ○1○○3♪◙ add eax, 4○○1○○1♪◙ jnz 0000E100 20 54 6F 70 4F 66 4C 6F 6F 70 09 09 30 20 2D 20 50 61 69 72 73 20 77 69 74 68 20 61 64 64 09 33 TopOfLoop○○0 - Pairs with add○3 0000E120 0D 0A 09 09 2D 2D 2D 2D 2D 2D 2D 09 2D 2D 2D 2D 2D 2D 2D 0D 0A 09 09 37 09 09 32 30 0D 0A 0D 0A ♪◙○○-------○-------♪◙○○7○○20♪◙♪◙ 0000E140 0D 0A 42 79 20 6D 6F 76 69 6E 67 20 74 68 65 20 69 6E 74 65 67 65 72 20 69 6E 73 74 72 75 63 74 ♪◙By moving the integer instruct 0000E160 69 6F 6E 73 20 62 65 74 77 65 65 6E 20 74 68 65 20 66 61 64 64 73 20 61 6E 64 20 66 73 74 70 73 ions between the fadds and fstps 0000E180 2C 20 62 6F 74 68 20 70 72 6F 63 65 73 73 6F 72 73 20 63 61 6E 20 65 78 65 63 75 74 65 20 74 68 , both processors can execute th 0000E1A0 65 20 69 6E 74 65 67 65 72 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 77 68 69 6C 65 20 74 68 65 e integer instructions while the 0000E1C0 20 66 61 64 64 73 20 69 73 20 63 6F 6D 70 6C 65 74 69 6E 67 20 69 6E 20 74 68 65 20 66 6C 6F 61 fadds is completing in the floa 0000E1E0 74 69 6E 67 2D 70 6F 69 6E 74 20 75 6E 69 74 20 61 6E 64 20 62 65 66 6F 72 65 20 74 68 65 20 66 ting-point unit and before the f 0000E200 73 74 70 73 20 62 65 67 69 6E 73 20 65 78 65 63 75 74 69 6F 6E 2E 20 4E 6F 74 65 20 74 68 61 74 stps begins execution. Note that 0000E220 20 74 68 69 73 20 6E 65 77 20 6C 6F 6F 70 20 73 74 72 75 63 74 75 72 65 20 72 65 71 75 69 72 65 this new loop structure require 0000E240 73 20 61 20 73 65 70 61 72 61 74 65 20 65 6E 74 72 79 20 70 6F 69 6E 74 20 66 6F 72 20 74 68 65 s a separate entry point for the 0000E260 20 66 69 72 73 74 20 69 74 65 72 61 74 69 6F 6E 20 62 65 63 61 75 73 65 20 74 68 65 20 6C 6F 6F first iteration because the loo 0000E280 70 20 6E 65 65 64 73 20 74 6F 20 62 65 67 69 6E 20 77 69 74 68 20 74 68 65 20 66 6C 64 73 2E 20 p needs to begin with the flds. 0000E2A0 41 6C 73 6F 2C 20 74 68 65 72 65 20 6E 65 65 64 73 20 74 6F 20 62 65 20 61 6E 20 61 64 64 69 74 Also, there needs to be an addit 0000E2C0 69 6F 6E 61 6C 20 66 73 74 70 73 20 61 66 74 65 72 20 74 68 65 20 63 6F 6E 64 69 74 69 6F 6E 61 ional fstps after the conditiona 0000E2E0 6C 20 6A 75 6D 70 20 74 6F 20 66 69 6E 69 73 68 20 74 68 65 20 66 69 6E 61 6C 20 6C 6F 6F 70 20 l jump to finish the final loop 0000E300 69 74 65 72 61 74 69 6F 6E 2E 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 0D 0A 31 2E 20 46 6C 6F 61 74 69 6E iteration.♪◙♪◙♪◙♪◙♪◙♪◙1. Floatin 0000E320 67 2D 50 6F 69 6E 74 20 53 74 6F 72 65 73 0D 0A 0D 0A 41 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 g-Point Stores♪◙♪◙A floating-poi 0000E340 6E 74 20 73 74 6F 72 65 20 6D 75 73 74 20 77 61 69 74 20 61 6E 20 65 78 74 72 61 20 63 79 63 6C nt store must wait an extra cycl 0000E360 65 20 66 6F 72 20 69 74 73 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 6F 70 65 72 61 6E 64 e for its floating-point operand 0000E380 2E 20 41 66 74 65 72 20 61 6E 20 66 6C 64 2C 20 61 6E 20 66 73 74 20 6D 75 73 74 20 77 61 69 74 . After an fld, an fst must wait 0000E3A0 20 6F 6E 65 20 63 6C 6F 63 6B 2E 20 41 66 74 65 72 20 74 68 65 20 63 6F 6D 6D 6F 6E 20 61 72 69 one clock. After the common ari 0000E3C0 74 68 6D 65 74 69 63 20 6F 70 65 72 61 74 69 6F 6E 73 2C 20 66 6D 75 6C 20 61 6E 64 20 66 61 64 thmetic operations, fmul and fad 0000E3E0 64 2C 20 77 68 69 63 68 20 6E 6F 72 6D 61 6C 6C 79 20 68 61 76 65 20 61 20 6C 61 74 65 6E 63 79 d, which normally have a latency 0000E400 20 6F 66 20 74 77 6F 2C 20 66 73 74 20 77 61 69 74 73 20 61 6E 20 65 78 74 72 61 20 63 79 63 6C of two, fst waits an extra cycl 0000E420 65 20 66 6F 72 20 61 20 74 6F 74 61 6C 20 6F 66 20 74 68 72 65 65 02 2E 0D 0A 0D 0A 09 66 6C 64 e for a total of three☻.♪◙♪◙○fld 0000E440 20 20 20 6D 65 6D 6C 09 3B 20 31 20 66 6C 64 20 74 61 6B 65 73 20 31 20 63 6C 6F 63 6B 0D 0A 09 meml○; 1 fld takes 1 clock♪◙○ 0000E460 09 3B 20 32 20 66 73 74 20 77 61 69 74 73 2C 20 73 63 68 65 64 75 6C 65 20 73 6F 6D 65 74 68 69 ○; 2 fst waits, schedule somethi 0000E480 6E 67 20 68 65 72 65 0D 0A 09 66 73 74 20 20 20 6D 65 6D 32 09 3B 20 33 2C 34 20 66 73 74 20 74 ng here♪◙○fst mem2○; 3,4 fst t 0000E4A0 61 6B 65 73 20 32 20 63 6C 6F 63 6B 73 0D 0A 0D 0A 09 66 61 64 64 20 20 6D 65 6D 6C 09 3B 20 31 akes 2 clocks♪◙♪◙○fadd meml○; 1 0000E4C0 20 61 64 64 20 74 61 6B 65 73 20 33 20 63 6C 6F 63 6B 73 0D 0A 09 09 3B 20 32 20 61 64 64 2C 20 add takes 3 clocks♪◙○○; 2 add, 0000E4E0 73 63 68 65 64 75 6C 65 20 73 6F 6D 65 74 68 69 6E 67 20 68 65 72 65 0D 0A 09 09 3B 20 33 20 61 schedule something here♪◙○○; 3 a 0000E500 64 64 2C 20 73 63 68 65 64 75 6C 65 20 73 6F 6D 65 74 68 69 6E 67 20 68 65 72 65 0D 0A 09 09 3B dd, schedule something here♪◙○○; 0000E520 20 34 20 66 73 74 20 77 61 69 74 73 2C 20 73 63 68 65 64 75 6C 65 20 73 6F 6D 65 74 68 69 6E 67 4 fst waits, schedule something 0000E540 20 68 65 72 65 0D 0A 09 66 73 74 20 20 20 6D 65 6D 32 09 3B 20 35 2C 32 20 66 73 74 20 74 61 6B here♪◙○fst mem2○; 5,2 fst tak 0000E560 65 73 20 32 20 63 6C 6F 63 6B 73 0D 0A 0D 0A 49 6E 20 74 68 65 20 6E 65 78 74 20 65 78 61 6D 70 es 2 clocks♪◙♪◙In the next examp 0000E580 6C 65 2C 20 74 68 65 20 73 74 6F 72 65 20 69 73 20 6E 6F 74 20 64 65 70 65 6E 64 65 6E 74 20 6F le, the store is not dependent o 0000E5A0 6E 20 74 68 65 20 70 72 65 76 69 6F 75 73 20 6C 6F 61 64 3A 0D 0A 0D 0A 09 66 6C 64 20 20 20 6D n the previous load:♪◙♪◙○fld m 0000E5C0 65 6D 6C 20 20 20 20 20 20 20 20 20 20 3A 20 31 0D 0A 09 66 6C 64 20 20 20 6D 65 6D 32 20 20 20 eml : 1♪◙○fld mem2 0000E5E0 20 20 20 20 20 20 20 3B 20 32 0D 0A 09 66 78 63 68 20 20 73 74 28 6C 29 20 20 20 20 20 20 20 20 ; 2♪◙○fxch st(l) 0000E600 20 3B 20 32 0D 0A 09 66 73 74 20 20 20 6D 65 6D 33 20 20 20 20 20 20 20 20 20 20 3B 20 33 20 73 ; 2♪◙○fst mem3 ; 3 s 0000E620 74 6F 72 65 73 20 76 61 6C 75 65 73 20 6C 6F 61 64 65 64 20 66 72 6F 6D 20 6D 65 6D 6C 0D 0A 0D tores values loaded from meml♪◙♪ 0000E640 0A 32 2E 20 41 20 72 65 67 69 73 74 65 72 20 6D 61 79 20 62 65 20 75 73 65 64 20 69 6D 6D 65 64 ◙2. A register may be used immed 0000E660 69 61 74 65 6C 79 20 61 66 74 65 72 20 69 74 20 68 61 73 20 62 65 65 6E 20 6C 6F 61 64 65 64 20 iately after it has been loaded 0000E680 28 77 69 74 68 20 66 6C 64 29 2E 0D 0A 0D 0A 09 66 6C 64 20 20 20 6D 65 6D 31 20 20 20 20 20 20 (with fld).♪◙♪◙○fld mem1 0000E6A0 20 20 20 20 3B 20 6C 0D 0A 09 66 61 64 64 20 20 6D 65 6D 32 20 20 20 20 20 20 20 20 20 20 3B 20 ; l♪◙○fadd mem2 ; 0000E6C0 32 2C 33 2C 34 0D 0A 0D 0A 33 2E 20 55 73 65 20 6F 66 20 61 20 72 65 67 69 73 74 65 72 20 62 79 2,3,4♪◙♪◙3. Use of a register by 0000E6E0 20 61 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 6F 70 65 72 61 74 69 6F 6E 20 69 6D 6D 65 a floating-point operation imme 0000E700 64 69 61 74 65 6C 79 20 61 66 74 65 72 20 69 74 20 68 61 73 20 62 65 65 6E 20 77 72 69 74 74 65 diately after it has been writte 0000E720 6E 20 62 79 20 61 6E 6F 74 68 65 72 20 66 61 64 64 2C 20 66 73 75 62 2C 20 6F 72 20 66 6D 75 6C n by another fadd, fsub, or fmul 0000E740 20 63 61 75 73 65 73 20 61 20 32 20 63 79 63 6C 65 20 64 65 6C 61 79 2E 20 49 66 20 69 6E 73 74 causes a 2 cycle delay. If inst 0000E760 72 75 63 74 69 6F 6E 73 20 61 72 65 20 69 6E 73 65 72 74 65 64 20 62 65 74 77 65 65 6E 20 74 68 ructions are inserted between th 0000E780 65 73 65 20 74 77 6F 2C 20 74 68 65 6E 20 6C 61 74 65 6E 63 79 20 61 6E 64 20 61 20 70 6F 74 65 ese two, then latency and a pote 0000E7A0 6E 74 69 61 6C 20 73 74 61 6C 6C 20 63 61 6E 20 62 65 20 68 69 64 64 65 6E 2E 0D 0A 0D 0A 34 2E ntial stall can be hidden.♪◙♪◙4. 0000E7C0 20 54 68 65 72 65 20 61 72 65 20 6D 75 6C 74 69 2D 63 79 63 6C 65 20 66 6C 6F 61 74 69 6E 67 2D There are multi-cycle floating- 0000E7E0 70 6F 69 6E 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 28 66 64 69 76 20 61 6E 64 20 66 73 71 point instructions (fdiv and fsq 0000E800 72 74 29 20 74 68 61 74 20 65 78 65 63 75 74 65 20 69 6E 20 74 68 65 20 66 6C 6F 61 74 69 6E 67 rt) that execute in the floating 0000E820 2D 70 6F 69 6E 74 20 75 6E 69 74 20 70 69 70 65 2E 20 57 68 69 6C 65 20 65 78 65 63 75 74 69 6E -point unit pipe. While executin 0000E840 67 20 74 68 65 73 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 69 6E 20 74 68 65 20 66 6C 6F 61 g these instructions in the floa 0000E860 74 69 6E 67 2D 70 6F 69 6E 74 20 75 6E 69 74 20 70 69 70 65 2C 20 69 6E 74 65 67 65 72 20 69 6E ting-point unit pipe, integer in 0000E880 73 74 72 75 63 74 69 6F 6E 73 20 63 61 6E 20 62 65 20 65 78 65 63 75 74 65 64 20 69 6E 20 70 61 structions can be executed in pa 0000E8A0 72 61 6C 6C 65 6C 2E 20 45 6D 69 74 74 69 6E 67 20 61 20 6E 75 6D 62 65 72 20 6F 66 20 69 6E 74 rallel. Emitting a number of int 0000E8C0 65 67 65 72 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 61 66 74 65 72 20 73 75 63 68 20 61 6E 20 eger instructions after such an 0000E8E0 69 6E 73 74 72 75 63 74 69 6F 6E 20 77 69 6C 6C 20 6B 65 65 70 20 74 68 65 20 69 6E 74 65 67 65 instruction will keep the intege 0000E900 72 20 65 78 65 63 75 74 69 6F 6E 20 75 6E 69 74 73 20 62 75 73 79 20 28 74 68 65 20 65 78 61 63 r execution units busy (the exac 0000E920 74 20 6E 75 6D 62 65 72 20 6F 66 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 64 65 70 65 6E 64 73 t number of instructions depends 0000E940 20 6F 6E 20 74 68 65 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 69 6E 73 74 72 75 63 74 69 on the floating-point instructi 0000E960 6F 6E 27 73 20 63 79 63 6C 65 20 63 6F 75 6E 74 29 2E 0D 0A 0D 0A 35 2E 20 54 68 65 20 69 6E 74 on's cycle count).♪◙♪◙5. The int 0000E980 65 67 65 72 20 6D 75 6C 74 69 70 6C 79 20 6F 70 65 72 61 74 69 6F 6E 73 2C 20 6D 75 6C 20 61 6E eger multiply operations, mul an 0000E9A0 64 20 69 6D 75 6C 2C 20 61 72 65 20 65 78 65 63 75 74 65 64 20 69 6E 20 74 68 65 20 66 6C 6F 61 d imul, are executed in the floa 0000E9C0 74 69 6E 67 2D 70 6F 69 6E 74 20 75 6E 69 74 20 73 6F 20 74 68 65 73 65 20 69 6E 73 74 72 75 63 ting-point unit so these instruc 0000E9E0 74 69 6F 6E 73 20 63 61 6E 6E 6F 74 20 62 65 20 65 78 65 63 75 74 65 64 20 69 6E 20 70 61 72 61 tions cannot be executed in para 0000EA00 6C 6C 65 6C 20 77 69 74 68 20 61 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 69 6E 73 74 72 llel with a floating-point instr 0000EA20 75 63 74 69 6F 6E 2E 0D 0A 0D 0A 36 2E 20 41 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 6D uction.♪◙♪◙6. A floating-point m 0000EA40 75 6C 74 69 70 6C 79 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 28 66 6D 75 6C 29 20 64 65 6C 61 79 ultiply instruction (fmul) delay 0000EA60 73 20 66 6F 72 20 6F 6E 65 20 63 79 63 6C 65 20 69 66 20 74 68 65 20 69 6D 6D 65 64 69 61 74 65 s for one cycle if the immediate 0000EA80 6C 79 20 70 72 65 63 65 64 69 6E 67 20 63 79 63 6C 65 20 65 78 65 63 75 74 65 64 20 61 6E 20 66 ly preceding cycle executed an f 0000EAA0 6D 75 6C 20 6F 72 20 61 6E 20 66 6D 75 6C 20 2F 20 66 78 63 68 20 70 61 69 72 2E 20 54 68 65 20 mul or an fmul / fxch pair. The 0000EAC0 6D 75 6C 74 69 70 6C 69 65 72 20 63 61 6E 20 6F 6E 6C 79 20 61 63 63 65 70 74 20 61 20 6E 65 77 multiplier can only accept a new 0000EAE0 20 70 61 69 72 20 6F 66 20 6F 70 65 72 61 6E 64 73 20 65 76 65 72 79 20 6F 74 68 65 72 20 63 79 pair of operands every other cy 0000EB00 63 6C 65 2E 0D 0A 0D 0A 37 2E 20 54 72 61 6E 73 63 65 6E 64 65 6E 74 61 6C 20 6F 70 65 72 61 74 cle.♪◙♪◙7. Transcendental operat 0000EB20 69 6F 6E 73 20 65 78 65 63 75 74 65 20 69 6E 20 74 68 65 20 55 20 70 69 70 65 20 61 6E 64 20 6E ions execute in the U pipe and n 0000EB40 6F 74 68 69 6E 67 20 63 61 6E 20 62 65 20 6F 76 65 72 6C 61 70 70 65 64 20 77 69 74 68 20 74 68 othing can be overlapped with th 0000EB60 65 6D 2C 20 73 6F 20 61 6E 20 69 6E 74 65 67 65 72 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 66 6F em, so an integer instruction fo 0000EB80 6C 6C 6F 77 69 6E 67 20 73 75 63 68 20 61 6E 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 77 69 6C 6C llowing such an instruction will 0000EBA0 20 77 61 69 74 20 75 6E 74 69 6C 20 74 68 61 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 63 6F 6D wait until that instruction com 0000EBC0 70 6C 65 74 65 73 2E 0D 0A 0D 0A 38 2E 20 46 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 6F 70 65 pletes.♪◙♪◙8. Floating-point ope 0000EBE0 72 61 74 69 6F 6E 73 20 74 68 61 74 20 74 61 6B 65 20 69 6E 74 65 67 65 72 20 6F 70 65 72 61 6E rations that take integer operan 0000EC00 64 73 20 28 66 69 61 64 64 20 6F 72 20 66 69 73 75 62 20 2E 2E 29 20 73 68 6F 75 6C 64 20 62 65 ds (fiadd or fisub ..) should be 0000EC20 20 61 76 6F 69 64 65 64 2E 20 54 68 65 73 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 73 68 6F avoided. These instructions sho 0000EC40 75 6C 64 20 62 65 20 73 70 6C 69 74 20 69 6E 74 6F 20 74 77 6F 20 69 6E 73 74 72 75 63 74 69 6F uld be split into two instructio 0000EC60 6E 73 3A 20 66 69 6C 64 20 61 6E 64 20 61 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 6F 70 ns: fild and a floating-point op 0000EC80 65 72 61 74 69 6F 6E 2E 20 54 68 65 20 6E 75 6D 62 65 72 20 6F 66 20 63 79 63 6C 65 73 20 62 65 eration. The number of cycles be 0000ECA0 66 6F 72 65 20 61 6E 6F 74 68 65 72 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 63 61 6E 20 62 65 20 fore another instruction can be 0000ECC0 69 73 73 75 65 64 20 28 74 68 72 6F 75 67 68 70 75 74 29 20 66 6F 72 20 66 69 61 64 64 20 69 73 issued (throughput) for fiadd is 0000ECE0 20 34 2C 20 77 68 69 6C 65 20 66 6F 72 20 66 69 6C 64 20 61 6E 64 20 73 69 6D 70 6C 65 20 66 6C 4, while for fild and simple fl 0000ED00 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 6F 70 20 69 74 20 69 73 20 31 2E 0D 0A 0D 0A 0D 0A 45 78 oating-point op it is 1.♪◙♪◙♪◙Ex 0000ED20 61 6D 70 6C 65 3A 0D 0A 0D 0A 43 6F 6D 70 6C 65 78 20 49 6E 73 74 72 75 63 74 69 6F 6E 73 20 20 ample:♪◙♪◙Complex Instructions 0000ED40 20 20 20 20 20 20 20 20 42 65 74 74 65 72 20 66 6F 72 20 50 6F 74 65 6E 74 69 61 6C 20 4F 76 65 Better for Potential Ove 0000ED60 72 6C 61 70 0D 0A 0D 0A 66 69 61 64 64 20 20 5B 65 62 70 5D 20 3B 20 34 20 20 20 20 20 20 20 20 rlap♪◙♪◙fiadd [ebp] ; 4 0000ED80 20 20 20 20 20 20 66 69 6C 64 20 20 20 5B 65 62 70 5D 20 20 3B 20 31 0D 0A 20 20 20 20 20 20 20 fild [ebp] ; 1♪◙ 0000EDA0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 66 61 64 64 70 20 20 73 74 faddp st 0000EDC0 28 6C 29 20 20 3B 20 32 0D 0A 0D 0A 55 73 69 6E 67 20 74 68 65 20 66 69 6C 64 20 2D 20 66 61 64 (l) ; 2♪◙♪◙Using the fild - fad 0000EDE0 64 70 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 79 69 65 6C 64 73 20 32 20 66 72 65 65 20 63 79 dp instructions yields 2 free cy 0000EE00 63 6C 65 73 20 66 6F 72 20 65 78 65 63 75 74 69 6E 67 20 6F 74 68 65 72 20 69 6E 73 74 72 75 63 cles for executing other instruc 0000EE20 74 69 6F 6E 73 2E 0D 0A 0D 0A 39 2E 20 54 68 65 20 66 73 74 73 77 20 69 6E 73 74 72 75 63 74 69 tions.♪◙♪◙9. The fstsw instructi 0000EE40 6F 6E 20 74 68 61 74 20 75 73 75 61 6C 6C 79 20 61 70 70 65 61 72 73 20 61 66 74 65 72 20 61 20 on that usually appears after a 0000EE60 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 63 6F 6D 70 61 72 69 73 6F 6E 20 69 6E 73 74 72 75 floating-point comparison instru 0000EE80 63 74 69 6F 6E 20 28 66 63 6F 6D 2C 20 66 63 6F 6D 70 2C 20 66 63 6F 6D 70 70 29 20 64 65 6C 61 ction (fcom, fcomp, fcompp) dela 0000EEA0 79 73 20 66 6F 72 20 33 20 63 79 63 6C 65 73 2E 20 4F 74 68 65 72 20 69 6E 73 74 72 75 63 74 69 ys for 3 cycles. Other instructi 0000EEC0 6F 6E 73 20 6D 61 79 20 62 65 20 69 6E 73 65 72 74 65 64 20 61 66 74 65 72 20 74 68 65 20 63 6F ons may be inserted after the co 0000EEE0 6D 70 61 72 69 73 6F 6E 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 69 6E 20 6F 72 64 65 72 20 74 6F mparison instruction in order to 0000EF00 20 68 69 64 65 20 74 68 65 20 6C 61 74 65 6E 63 79 2E 0D 0A 0D 0A 31 30 2E 20 4D 6F 76 69 6E 67 hide the latency.♪◙♪◙10. Moving 0000EF20 20 61 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 6D 65 6D 6F 72 79 2F 69 6D 6D 65 64 69 61 a floating-point memory/immedia 0000EF40 74 65 20 74 6F 20 6D 65 6D 6F 72 79 20 73 68 6F 75 6C 64 20 62 65 20 64 6F 6E 65 20 62 79 20 69 te to memory should be done by i 0000EF60 6E 74 65 67 65 72 20 6D 6F 76 65 73 20 28 69 66 20 70 72 65 63 69 73 69 6F 6E 20 63 6F 6E 76 65 nteger moves (if precision conve 0000EF80 72 73 69 6F 6E 20 69 73 20 6E 6F 74 20 6E 65 65 64 65 64 29 20 69 6E 73 74 65 61 64 20 6F 66 20 rsion is not needed) instead of 0000EFA0 64 6F 69 6E 67 20 66 6C 64 20 2D 20 66 73 74 70 2E 0D 0A 0D 0A 45 78 61 6D 70 6C 65 73 20 66 6F doing fld - fstp.♪◙♪◙Examples fo 0000EFC0 72 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 6D 6F 76 65 73 3A 0D 0A 0D 0A 64 6F 75 62 6C r floating-point moves:♪◙♪◙doubl 0000EFE0 65 20 70 72 65 63 69 73 69 6F 6E 3A 20 34 20 76 73 2E 20 32 20 63 79 63 6C 65 73 0D 0A 0D 0A 20 e precision: 4 vs. 2 cycles♪◙♪◙ 0000F000 20 20 20 20 20 20 20 66 6C 64 20 20 5B 65 62 70 5D 20 20 20 20 20 3B 20 31 20 20 20 20 20 20 20 fld [ebp] ; 1 0000F020 20 20 20 20 6D 6F 76 20 20 65 61 78 2C 20 5B 65 62 70 5D 20 20 20 20 20 20 20 20 3B 20 31 0D 0A mov eax, [ebp] ; 1♪◙ 0000F040 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 3B 20 32 20 20 20 20 20 20 ; 2 0000F060 20 20 20 20 20 6D 6F 76 20 20 65 64 78 2C 20 5B 65 62 70 2B 34 5D 20 20 20 20 20 20 3B 20 31 0D mov edx, [ebp+4] ; 1♪ 0000F080 0A 20 20 20 20 20 20 20 20 66 73 74 70 20 5B 65 64 69 5D 20 20 20 20 20 3B 20 33 2C 34 20 20 20 ◙ fstp [edi] ; 3,4 0000F0A0 20 20 20 20 20 20 6D 6F 76 20 20 5B 65 64 69 5D 2C 20 65 61 78 20 20 20 20 20 20 20 20 3B 20 32 mov [edi], eax ; 2 0000F0C0 0D 0A 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ♪◙ 0000F0E0 20 20 20 20 20 20 20 6D 6F 76 20 20 5B 65 64 69 2B 34 5D 2C 20 65 64 78 20 20 20 20 20 20 3B 20 mov [edi+4], edx ; 0000F100 32 0D 0A 0D 0A 20 20 20 20 73 69 6E 67 6C 65 20 70 72 65 63 69 73 69 6F 6E 3A 20 34 20 76 73 2E 2♪◙♪◙ single precision: 4 vs. 0000F120 20 32 20 63 79 63 6C 65 73 0D 0A 0D 0A 20 20 20 20 20 20 20 20 20 20 20 20 66 6C 64 20 20 5B 65 2 cycles♪◙♪◙ fld [e 0000F140 62 70 5D 20 20 20 20 20 3B 20 31 20 20 20 20 20 20 20 20 20 20 20 6D 6F 76 20 20 65 61 78 2C 20 bp] ; 1 mov eax, 0000F160 5B 65 62 70 5D 20 20 20 20 20 20 20 20 3B 20 31 0D 0A 20 20 20 20 20 20 20 20 20 20 20 20 20 20 [ebp] ; 1♪◙ 0000F180 20 20 20 20 20 20 20 20 20 3B 20 32 20 20 20 20 20 20 20 20 20 20 20 6D 6F 76 20 20 5B 65 64 69 ; 2 mov [edi 0000F1A0 5D 2C 20 65 61 78 20 20 20 20 20 20 20 20 3B 20 32 0D 0A 20 20 20 20 20 20 20 20 66 73 74 70 20 ], eax ; 2♪◙ fstp 0000F1C0 5B 65 64 69 5D 20 20 20 20 20 3B 20 33 2C 34 0D 0A 0D 0A 54 68 69 73 20 6F 70 74 69 6D 69 7A 61 [edi] ; 3,4♪◙♪◙This optimiza 0000F1E0 74 69 6F 6E 20 61 6C 73 6F 20 61 70 70 6C 69 65 73 20 74 6F 20 74 68 65 20 49 6E 74 65 6C 34 38 tion also applies to the Intel48 0000F200 36 20 70 72 6F 63 65 73 73 6F 72 2E 0D 0A 0D 0A 31 31 2E 20 54 72 61 6E 73 63 65 6E 64 65 6E 74 6 processor.♪◙♪◙11. Transcendent 0000F220 61 6C 20 6F 70 65 72 61 74 69 6F 6E 73 20 65 78 65 63 75 74 65 20 6F 6E 20 74 68 65 20 50 65 6E al operations execute on the Pen 0000F240 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 20 6D 75 63 68 20 66 61 73 74 65 72 20 74 68 61 6E 20 tium processor much faster than 0000F260 6F 6E 20 74 68 65 20 49 6E 74 65 6C 34 38 36 20 70 72 6F 63 65 73 73 6F 72 2E 20 20 49 74 20 6D on the Intel486 processor. It m 0000F280 61 79 20 62 65 20 77 6F 72 74 68 77 68 69 6C 65 20 69 6E 6C 69 6E 69 6E 67 20 73 6F 6D 65 20 6F ay be worthwhile inlining some o 0000F2A0 66 20 74 68 65 73 65 20 6D 61 74 68 20 6C 69 62 72 61 72 79 20 63 61 6C 6C 73 20 62 65 63 61 75 f these math library calls becau 0000F2C0 73 65 20 6F 66 20 74 68 65 20 66 61 63 74 20 74 68 61 74 20 74 68 65 20 63 61 6C 6C 20 61 6E 64 se of the fact that the call and 0000F2E0 20 70 72 6F 6C 6F 67 75 65 2F 65 70 69 6C 6F 67 75 65 20 6F 76 65 72 68 65 61 64 20 69 6E 76 6F prologue/epilogue overhead invo 0000F300 6C 76 65 64 20 77 69 74 68 20 74 68 65 20 6C 69 62 72 61 72 79 20 63 61 6C 6C 73 20 69 73 20 6E lved with the library calls is n 0000F320 6F 20 6C 6F 6E 67 65 72 20 6E 65 67 6C 69 67 69 62 6C 65 2E 20 20 45 6D 75 6C 61 74 69 6E 67 20 o longer negligible. Emulating 0000F340 74 68 65 73 65 20 6F 70 65 72 61 74 69 6F 6E 73 20 69 6E 20 73 6F 66 74 77 61 72 65 20 77 69 6C these operations in software wil 0000F360 6C 20 6E 6F 74 20 62 65 20 66 61 73 74 65 72 20 74 68 61 6E 20 74 68 65 20 68 61 72 64 77 61 72 l not be faster than the hardwar 0000F380 65 20 75 6E 6C 65 73 73 20 61 63 63 75 72 61 63 79 20 69 73 20 73 61 63 72 69 66 69 63 65 64 2E e unless accuracy is sacrificed. 0000F3A0 0D 0A 0D 0A 31 32 2E 20 49 6E 74 65 67 65 72 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 67 65 6E ♪◙♪◙12. Integer instructions gen 0000F3C0 65 72 61 6C 6C 79 20 6F 76 65 72 6C 61 70 20 77 69 74 68 20 74 68 65 20 66 6C 6F 61 74 69 6E 67 erally overlap with the floating 0000F3E0 2D 70 6F 69 6E 74 20 6F 70 65 72 61 74 69 6F 6E 73 20 65 78 63 65 70 74 20 77 68 65 6E 20 74 68 -point operations except when th 0000F400 65 20 6C 61 73 74 0D 0A 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 6F 70 65 72 61 74 69 6F 6E e last♪◙floating-point operation 0000F420 20 77 61 73 20 66 78 63 68 2E 20 49 6E 20 74 68 69 73 20 63 61 73 65 20 74 68 65 72 65 20 69 73 was fxch. In this case there is 0000F440 20 61 20 6F 6E 65 20 63 79 63 6C 65 20 64 65 6C 61 79 2E 0D 0A 0D 0A 09 55 20 70 69 70 65 20 20 a one cycle delay.♪◙♪◙○U pipe 0000F460 20 09 20 20 20 20 20 20 20 20 09 56 20 20 70 69 70 65 09 09 0D 0A 0D 0A 09 66 61 64 64 20 20 20 ○ ○V pipe○○♪◙♪◙○fadd 0000F480 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 66 78 63 68 20 20 20 20 20 20 20 20 20 20 20 20 20 fxch 0000F4A0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 3B 20 31 0D 0A 20 20 20 20 20 20 20 20 20 20 20 20 20 ; 1♪◙ 0000F4C0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 0000F4E0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 3B 20 32 20 66 78 63 68 20 64 65 6C 61 79 0D 0A 09 ; 2 fxch delay♪◙○ 0000F500 6D 6F 76 20 20 20 65 61 78 2C 20 31 20 20 20 20 20 20 20 20 20 20 69 6E 63 20 20 20 20 20 20 20 mov eax, 1 inc 0000F520 65 64 78 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 3B 20 33 0D 0A 20 0D 0A 0C 37 2E edx ; 3♪◙ ♪◙♀7. 0000F540 20 53 75 6D 6D 61 72 79 0D 0A 0D 0A 54 68 65 20 66 6F 6C 6C 6F 77 69 6E 67 20 74 61 62 6C 65 73 Summary♪◙♪◙The following tables 0000F560 20 73 75 6D 6D 61 72 69 7A 65 20 74 68 65 20 6D 69 63 72 6F 20 61 72 63 68 69 74 65 63 74 75 72 summarize the micro architectur 0000F580 65 20 64 69 66 66 65 72 65 6E 63 65 73 20 61 6D 6F 6E 67 20 49 6E 74 65 6C 33 38 36 2C 20 49 6E e differences among Intel386, In 0000F5A0 74 65 6C 34 38 36 20 61 6E 64 20 50 65 6E 74 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 73 20 61 6E tel486 and Pentium processors an 0000F5C0 64 20 74 68 65 20 63 6F 72 72 65 73 70 6F 6E 64 69 6E 67 20 63 6F 64 65 20 67 65 6E 65 72 61 74 d the corresponding code generat 0000F5E0 69 6F 6E 20 63 6F 6E 73 69 64 65 72 61 74 69 6F 6E 2E 20 49 74 20 69 73 20 70 6F 73 73 69 62 6C ion consideration. It is possibl 0000F600 65 20 74 6F 20 64 65 72 69 76 65 20 61 20 73 65 74 20 6F 66 20 63 6F 64 65 20 67 65 6E 65 72 61 e to derive a set of code genera 0000F620 74 69 6F 6E 20 73 74 72 61 74 65 67 69 65 73 20 74 68 61 74 20 70 72 6F 76 69 64 65 20 74 68 65 tion strategies that provide the 0000F640 20 6F 70 74 69 6D 61 6C 20 70 65 72 66 6F 72 6D 61 6E 63 65 20 61 63 72 6F 73 73 20 74 68 65 20 optimal performance across the 0000F660 76 61 72 69 6F 75 73 20 6D 65 6D 62 65 72 73 20 6F 66 20 74 68 65 20 49 6E 74 65 6C 33 38 36 20 various members of the Intel386 0000F680 70 72 6F 63 65 73 73 6F 72 20 66 61 6D 69 6C 79 20 65 78 63 65 70 74 20 66 6F 72 20 74 68 65 20 processor family except for the 0000F6A0 75 73 65 20 6F 66 20 46 58 43 48 20 74 6F 20 6D 61 78 69 6D 69 7A 65 20 74 68 65 20 50 65 6E 74 use of FXCH to maximize the Pent 0000F6C0 69 75 6D 20 70 72 6F 63 65 73 73 6F 72 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 74 68 72 ium processor floating-point thr 0000F6E0 6F 75 67 68 70 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72 65 64 20 62 75 73 20 74 6F 20 63 61 63 68 access♪•2x6b shared bus to cach 0000F7E0 65 0D 07 34 78 33 32 62 20 70 72 69 76 61 74 65 20 62 75 73 20 74 6F 20 63 61 63 68 65 0D 07 0D e♪•4x32b private bus to cache♪•♪ 0000F800 07 44 65 63 6F 64 65 72 0D 07 33 20 64 65 65 70 20 64 65 63 6F 64 65 64 20 46 49 46 4F 0D 07 70 •Decoder♪•3 deep decoded FIFO♪•p 0000F820 61 72 74 20 6F 66 20 63 6F 72 65 20 70 69 70 65 6C 69 6E 65 0D 07 70 61 72 74 20 6F 66 20 63 6F art of core pipeline♪•part of co 0000F840 72 65 20 70 69 70 65 6C 69 6E 65 0D 07 0D 07 43 6F 72 65 0D 07 73 6F 6D 65 20 69 6E 73 74 72 75 re pipeline♪•♪•Core♪•some instru 0000F860 63 74 69 6F 6E 20 6F 76 65 72 6C 61 70 0D 07 35 20 73 74 61 67 65 73 20 70 69 70 65 6C 69 6E 65 ction overlap♪•5 stages pipeline 0000F880 0D 07 35 20 73 74 61 67 65 73 20 70 69 70 65 6C 69 6E 65 20 26 20 73 75 70 65 72 73 63 61 6C 61 ♪•5 stages pipeline & superscala 0000F8A0 72 0D 07 0D 07 4D 61 74 68 0D 07 43 6F 2D 70 72 6F 63 65 73 73 6F 72 0D 07 4F 6E 2D 43 68 69 70 r♪•♪•Math♪•Co-processor♪•On-Chip 0000F8C0 0D 07 4F 6E 2D 43 68 69 70 20 26 20 70 69 70 65 6C 69 6E 65 64 0D 07 0D 07 0D 0A 20 0D 0A 50 72 ♪•On-Chip & pipelined♪•♪•♪◙ ♪◙Pr 0000F8E0 6F 63 65 73 73 6F 72 20 43 68 61 72 61 63 74 65 72 69 73 74 69 63 73 0D 07 4F 70 74 69 6D 69 7A ocessor Characteristics♪•Optimiz 0000F900 61 74 69 6F 6E 73 0D 07 49 6E 74 65 6C 33 38 36 20 50 72 6F 63 65 73 73 6F 72 0D 07 49 6E 74 65 ations♪•Intel386 Processor♪•Inte 0000F920 6C 34 38 36 20 50 72 6F 63 65 73 73 6F 72 0D 07 50 65 6E 74 69 75 6D 20 50 72 6F 63 65 73 73 6F l486 Processor♪•Pentium Processo 0000F940 72 0D 07 0D 07 43 61 63 68 65 0D 07 49 6E 74 65 72 6C 65 61 76 65 20 6D 65 6D 20 77 69 74 68 20 r♪•♪•Cache♪•Interleave mem with 0000F960 6E 6F 6E 2D 6D 65 6D 0D 07 64 6F 6E 27 74 20 63 61 72 65 0D 07 49 6E 74 65 72 6C 65 61 76 65 20 non-mem♪•don't care♪•Interleave 0000F980 69 66 20 34 20 63 6F 6E 73 65 63 75 74 69 76 65 0D 07 64 6F 6E 27 74 20 63 61 72 65 0D 07 0D 07 if 4 consecutive♪•don't care♪•♪• 0000F9A0 50 72 65 66 65 74 63 68 65 72 0D 07 41 6C 69 67 6E 6D 65 6E 74 0D 07 30 2D 4D 4F 44 2D 34 0D 07 Prefetcher♪•Alignment♪•0-MOD-4♪• 0000F9C0 30 2D 4D 4F 44 2D 31 36 0D 07 64 6F 6E 27 74 20 63 61 72 65 0D 07 0D 07 50 69 70 65 6C 69 6E 65 0-MOD-16♪•don't care♪•♪•Pipeline 0000F9E0 64 20 45 78 65 63 75 74 69 6F 6E 20 63 6F 72 65 0D 07 42 61 73 65 20 56 73 20 69 6E 64 65 78 0D d Execution core♪•Base Vs index♪ 0000FA00 07 64 6F 6E 27 74 20 63 61 72 65 0D 07 75 73 65 20 62 61 73 65 0D 07 64 6F 6E 27 74 20 63 61 72 •don't care♪•use base♪•don't car 0000FA20 65 0D 07 0D 07 0D 07 41 76 6F 69 64 20 41 47 49 0D 07 64 6F 6E 27 74 20 63 61 72 65 0D 07 6E 65 e♪•♪•♪•Avoid AGI♪•don't care♪•ne 0000FA40 78 74 20 69 6E 73 74 72 0D 07 6E 65 78 74 20 33 20 69 6E 73 74 72 0D 07 0D 07 0D 07 49 6E 73 74 xt instr♪•next 3 instr♪•♪•♪•Inst 0000FA60 72 75 63 74 69 6F 6E 20 73 65 6C 65 63 74 69 6F 6E 0D 07 31 20 63 6C 6B 20 70 65 6E 61 6C 74 79 ruction selection♪•1 clk penalty 0000FA80 0D 07 73 68 6F 72 74 20 69 6E 73 74 72 0D 07 73 68 6F 72 74 20 69 6E 73 74 72 0D 07 0D 07 53 75 ♪•short instr♪•short instr♪•♪•Su 0000FAA0 70 65 72 73 63 61 6C 61 72 0D 07 50 61 69 72 69 6E 67 0D 07 64 6F 6E 27 74 20 63 61 72 65 0D 07 perscalar♪•Pairing♪•don't care♪• 0000FAC0 64 6F 6E 27 74 20 63 61 72 65 0D 07 70 61 69 72 0D 07 0D 07 50 69 70 65 6C 69 6E 65 64 20 46 50 don't care♪•pair♪•♪•Pipelined FP 0000FAE0 55 20 77 69 74 68 20 46 58 43 48 0D 07 6D 6F 72 65 20 73 63 68 65 64 75 6C 69 6E 67 0D 07 31 38 U with FXCH♪•more scheduling♪•18 0000FB00 20 63 6C 6B 20 70 65 6E 61 6C 74 79 0D 07 34 20 63 6C 6B 20 70 65 6E 61 6C 74 79 0D 07 73 63 68 clk penalty♪•4 clk penalty♪•sch 0000FB20 65 64 75 6C 65 0D 07 0D 07 0D 0A 0D 0A 52 65 63 6F 6D 6D 65 6E 64 61 74 69 6F 6E 73 20 66 6F 72 edule♪•♪•♪◙♪◙Recommendations for 0000FB40 20 42 6C 65 6E 64 65 64 3A 0D 0A 0D 0A 31 2E 20 49 6E 74 65 72 6C 65 61 76 65 20 6D 65 6D 20 77 Blended:♪◙♪◙1. Interleave mem w 0000FB60 69 74 68 20 6E 6F 6E 2D 6D 65 6D 3A 20 64 6F 20 6E 6F 74 68 69 6E 67 0D 0A 0D 0A 32 2E 20 43 6F ith non-mem: do nothing♪◙♪◙2. Co 0000FB80 64 65 20 61 6C 69 67 6E 6D 65 6E 74 3A 20 30 2D 6D 6F 64 2D 31 36 20 6F 6E 20 6C 6F 6F 70 0D 0A de alignment: 0-mod-16 on loop♪◙ 0000FBA0 0D 0A 33 2E 20 42 61 73 65 20 56 73 20 69 6E 64 65 78 3A 20 75 73 65 20 62 61 73 65 0D 0A 0D 0A ♪◙3. Base Vs index: use base♪◙♪◙ 0000FBC0 34 2E 20 41 76 6F 69 64 20 41 47 49 3A 20 6E 65 78 74 20 33 20 69 6E 73 74 72 75 63 74 69 6F 6E 4. Avoid AGI: next 3 instruction 0000FBE0 73 0D 0A 0D 0A 35 2E 20 49 6E 73 74 72 75 63 74 69 6F 6E 20 73 65 6C 65 63 74 69 6F 6E 3A 20 73 s♪◙♪◙5. Instruction selection: s 0000FC00 68 6F 72 74 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 73 65 71 75 65 6E 63 65 0D 0A 0D 0A 36 2E hort instructions sequence♪◙♪◙6. 0000FC20 20 50 61 69 72 69 6E 67 3A 20 70 61 69 72 0D 0A 0D 0A 37 2E 20 46 50 20 73 63 68 65 64 75 6C 69 Pairing: pair♪◙♪◙7. FP scheduli 0000FC40 6E 67 3A 20 61 76 6F 69 64 20 46 58 43 48 0D 0A 0C 41 70 70 65 6E 64 69 78 20 13 52 65 66 20 5C ng: avoid FXCH♪◙♀Appendix ‼Ref \ 0000FC60 2A 20 63 68 61 72 66 6F 72 6D 61 74 20 43 68 61 70 4E 75 6D 14 41 15 0B 13 43 68 61 70 74 69 74 * charformat ChapNum¶A§♂‼Chaptit 0000FC80 6C 65 20 5C 2A 20 63 68 61 72 66 6F 72 6D 61 74 14 49 6E 73 74 72 75 63 74 69 6F 6E 20 50 61 69 le \* charformat¶Instruction Pai 0000FCA0 72 69 6E 67 20 53 75 6D 6D 61 72 79 15 0D 0A 0D 0A 0D 0A 54 68 65 20 66 6F 6C 6C 6F 77 69 6E 67 ring Summary§♪◙♪◙♪◙The following 0000FCC0 20 61 62 62 72 65 76 69 61 74 69 6F 6E 73 20 61 72 65 20 75 73 65 64 20 69 6E 20 74 68 65 20 50 abbreviations are used in the P 0000FCE0 61 69 72 69 6E 67 20 63 6F 6C 75 6D 6E 20 6F 66 20 74 68 65 20 69 6E 74 65 67 65 72 20 74 61 62 airing column of the integer tab 0000FD00 6C 65 20 69 6E 20 74 68 69 73 20 41 70 70 65 6E 64 69 78 3A 0D 0A 4E 50 09 97 20 4E 6F 74 20 70 le in this Appendix:♪◙NP○ù Not p 0000FD20 61 69 72 61 62 6C 65 2C 20 65 78 65 63 75 74 65 73 20 69 6E 20 55 20 70 69 70 65 0D 0A 50 55 09 airable, executes in U pipe♪◙PU○ 0000FD40 97 20 50 61 69 72 61 62 6C 65 20 69 66 20 69 73 73 75 65 64 20 74 6F 20 55 20 70 69 70 65 0D 0A ù Pairable if issued to U pipe♪◙ 0000FD60 50 56 09 97 20 50 61 69 72 61 62 6C 65 20 69 66 20 69 73 73 75 65 64 20 74 6F 20 56 20 70 69 70 PV○ù Pairable if issued to V pip 0000FD80 65 0D 0A 55 56 09 97 20 50 61 69 72 61 62 6C 65 20 69 6E 20 65 69 74 68 65 72 20 70 69 70 65 0D e♪◙UV○ù Pairable in either pipe♪ 0000FDA0 0A 0D 0A 0D 0A 49 6E 20 74 68 65 20 66 6C 6F 61 74 69 6E 67 2D 70 6F 69 6E 74 20 74 61 62 6C 65 ◙♪◙♪◙In the floating-point table 0000FDC0 20 69 6E 20 74 68 69 73 20 41 70 70 65 6E 64 69 78 3A 0D 0A 46 58 09 97 20 50 61 69 72 73 20 77 in this Appendix:♪◙FX○ù Pairs w 0000FDE0 69 74 68 20 46 58 43 48 0D 0A 4E 50 09 97 20 4E 6F 20 70 61 69 72 69 6E 67 2E 0D 0A 0D 0A 54 68 ith FXCH♪◙NP○ù No pairing.♪◙♪◙Th 0000FE00 65 20 49 2F 4F 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 20 61 72 65 20 6E 6F 74 20 70 61 69 72 61 e I/O instructions are not paira 0000FE20 62 6C 65 2E 20 0D 0A 49 6E 74 65 67 65 72 20 49 6E 73 74 72 75 63 74 69 6F 6E 20 50 61 69 72 69 ble. ♪◙Integer Instruction Pairi 0000FE40 6E 67 0D 0A 49 4E 53 54 52 55 43 54 49 4F 4E 09 46 4F 52 4D 41 54 0D 07 50 61 69 72 69 6E 67 0D ng♪◙INSTRUCTION○FORMAT♪•Pairing♪ 0000FE60 07 0D 07 41 41 41 20 96 20 41 53 43 49 49 20 41 64 6A 75 73 74 20 61 66 74 65 72 20 41 64 64 69 •♪•AAA û ASCII Adjust after Addi 0000FE80 74 69 6F 6E 0D 07 4E 50 0D 07 0D 07 41 41 44 20 96 20 41 53 43 49 49 20 41 64 6A 75 73 74 20 41 tion♪•NP♪•♪•AAD û ASCII Adjust A 0000FEA0 58 20 62 65 66 6F 72 65 20 44 69 76 69 73 69 6F 6E 0D 07 4E 50 0D 07 0D 07 41 41 4D 20 96 20 41 X before Division♪•NP♪•♪•AAM û A 0000FEC0 53 43 49 49 20 41 64 6A 75 73 74 20 41 58 20 61 66 74 65 72 20 4D 75 6C 74 69 70 6C 79 0D 07 4E SCII Adjust AX after Multiply♪•N 0000FEE0 50 0D 07 0D 07 41 41 53 20 96 20 41 53 43 49 49 20 41 64 6A 75 73 74 20 41 4C 20 61 66 74 65 72 P♪•♪•AAS û ASCII Adjust AL after 0000FF00 20 53 75 62 74 72 61 63 74 69 6F 6E 0D 07 4E 50 0D 07 0D 07 41 44 43 20 96 20 41 44 44 20 77 69 Subtraction♪•NP♪•♪•ADC û ADD wi 0000FF20 74 68 20 43 61 72 72 79 0D 07 50 55 0D 07 0D 07 41 44 44 20 96 20 41 64 64 0D 07 55 56 0D 07 0D th Carry♪•PU♪•♪•ADD û Add♪•UV♪•♪ 0000FF40 07 41 4E 44 20 96 20 4C 6F 67 69 63 61 6C 20 41 4E 44 0D 07 55 56 0D 07 0D 07 41 52 50 4C 20 96 •AND û Logical AND♪•UV♪•♪•ARPL û 0000FF60 20 41 64 6A 75 73 74 20 52 50 4C 20 46 69 65 6C 64 20 6F 66 20 53 65 6C 65 63 74 6F 72 0D 07 4E Adjust RPL Field of Selector♪•N 0000FF80 50 0D 07 0D 07 42 4F 55 4E 44 20 96 20 43 68 65 63 6B 20 41 72 72 61 79 20 41 67 61 69 6E 73 74 P♪•♪•BOUND û Check Array Against 0000FFA0 20 42 6F 75 6E 64 73 0D 07 4E 50 0D 07 0D 07 42 53 46 20 96 20 42 69 74 20 53 63 61 6E 20 46 6F Bounds♪•NP♪•♪•BSF û Bit Scan Fo 0000FFC0 72 77 61 72 64 0D 07 4E 50 0D 07 0D 07 42 53 52 20 96 20 42 69 74 20 53 63 61 6E 20 52 65 76 65 rward♪•NP♪•♪•BSR û Bit Scan Reve 0000FFE0 72 73 65 0D 07 4E 50 0D 07 0D 07 42 53 57 41 50 20 96 20 42 79 74 65 20 53 77 61 70 0D 07 4E 50 rse♪•NP♪•♪•BSWAP û Byte Swap♪•NP 00010000 0D 07 0D 07 42 54 20 96 20 42 69 74 20 54 65 73 74 0D 07 4E 50 0D 07 0D 07 42 54 43 20 96 20 42 ♪•♪•BT û Bit Test♪•NP♪•♪•BTC û B 00010020 69 74 20 54 65 73 74 20 61 6E 64 20 43 6F 6D 70 6C 65 6D 65 6E 74 0D 07 4E 50 0D 07 0D 07 42 54 it Test and Complement♪•NP♪•♪•BT 00010040 52 20 96 20 42 69 74 20 54 65 73 74 20 61 6E 64 20 52 65 73 65 74 0D 07 4E 50 0D 07 0D 07 42 54 R û Bit Test and Reset♪•NP♪•♪•BT 00010060 53 20 96 20 42 69 74 20 54 65 73 74 20 61 6E 64 20 53 65 74 0D 07 4E 50 0D 07 0D 07 43 41 4C 4C S û Bit Test and Set♪•NP♪•♪•CALL 00010080 20 96 20 43 61 6C 6C 20 50 72 6F 63 65 64 75 72 65 20 28 69 6E 20 73 61 6D 65 20 73 65 67 6D 65 û Call Procedure (in same segme 000100A0 6E 74 29 0D 07 0D 07 0D 07 A0 A0 A0 64 69 72 65 63 74 09 31 31 31 30 20 31 30 30 30 20 3A 20 66 nt)♪•♪•♪•ááádirect○1110 1000 : f 000100C0 75 6C 6C 20 64 69 73 70 6C 61 63 65 6D 65 6E 74 0D 07 50 56 0D 07 0D 07 A0 A0 A0 72 65 67 69 73 ull displacement♪•PV♪•♪•áááregis 000100E0 74 65 72 20 69 6E 64 69 72 65 63 74 09 31 31 31 31 20 31 31 31 31 20 3A 20 31 31 20 30 31 30 20 ter indirect○1111 1111 : 11 010 00010100 72 65 67 0D 07 4E 50 0D 07 0D 07 A0 A0 A0 6D 65 6D 6F 72 79 20 69 6E 64 69 72 65 63 74 09 31 31 reg♪•NP♪•♪•ááámemory indirect○11 00010120 31 31 20 31 31 31 31 20 3A 20 6D 6F 64 20 30 31 30 20 72 2F 6D 0D 07 4E 50 0D 07 0D 07 43 41 4C 11 1111 : mod 010 r/m♪•NP♪•♪•CAL 00010140 4C 20 96 20 43 61 6C 6C 20 50 72 6F 63 65 64 75 72 65 20 28 69 6E 20 6F 74 68 65 72 20 73 65 67 L û Call Procedure (in other seg 00010160 6D 65 6E 74 29 0D 07 4E 50 0D 07 0D 07 43 42 57 20 96 20 43 6F 6E 76 65 72 74 20 42 79 74 65 20 ment)♪•NP♪•♪•CBW û Convert Byte 00010180 74 6F 20 57 6F 72 64 20 0B 43 57 44 45 20 96 20 43 6F 6E 76 65 72 74 20 57 6F 72 64 20 74 6F 20 to Word ♂CWDE û Convert Word to 000101A0 44 6F 75 62 6C 65 77 6F 72 64 0D 07 4E 50 0D 07 0D 07 43 4C 43 20 96 20 43 6C 65 61 72 20 43 61 Doubleword♪•NP♪•♪•CLC û Clear Ca 000101C0 72 72 79 20 46 6C 61 67 0D 07 4E 50 0D 07 0D 07 43 4C 44 20 96 20 43 6C 65 61 72 20 44 69 72 65 rry Flag♪•NP♪•♪•CLD û Clear Dire 000101E0 63 74 69 6F 6E 20 46 6C 61 67 0D 07 4E 50 0D 07 0D 07 43 4C 49 20 96 20 43 6C 65 61 72 20 49 6E ction Flag♪•NP♪•♪•CLI û Clear In 00010200 74 65 72 72 75 70 74 20 46 6C 61 67 0D 07 4E 50 0D 07 0D 07 43 4C 54 53 20 96 20 43 6C 65 61 72 terrupt Flag♪•NP♪•♪•CLTS û Clear 00010220 20 54 61 73 6B 2D 53 77 69 74 63 68 65 64 20 46 6C 61 67 20 69 6E 20 43 52 30 0D 07 4E 50 0D 07 Task-Switched Flag in CR0♪•NP♪• 00010240 0D 07 43 4D 43 20 96 20 43 6F 6D 70 6C 65 6D 65 6E 74 20 43 61 72 72 79 20 46 6C 61 67 0D 07 4E ♪•CMC û Complement Carry Flag♪•N 00010260 50 0D 07 0D 07 43 4D 50 20 96 20 43 6F 6D 70 61 72 65 20 54 77 6F 20 4F 70 65 72 61 6E 64 73 0D P♪•♪•CMP û Compare Two Operands♪ 00010280 07 55 56 0D 07 0D 07 43 4D 50 53 2F 43 4D 50 53 42 2F 43 4D 50 53 57 2F 43 4D 50 53 44 20 96 20 •UV♪•♪•CMPS/CMPSB/CMPSW/CMPSD û 000102A0 43 6F 6D 70 61 72 65 20 53 74 72 69 6E 67 20 4F 70 65 72 61 6E 64 73 0D 07 4E 50 0D 07 0D 07 43 Compare String Operands♪•NP♪•♪•C 000102C0 4D 50 58 43 48 47 20 96 20 43 6F 6D 70 61 72 65 20 61 6E 64 20 45 78 63 68 61 6E 67 65 20 0D 07 MPXCHG û Compare and Exchange ♪• 000102E0 4E 50 0D 07 0D 07 43 4D 50 58 43 48 47 38 42 20 96 20 43 6F 6D 70 61 72 65 20 61 6E 64 20 45 78 NP♪•♪•CMPXCHG8B û Compare and Ex 00010300 63 68 61 6E 67 65 20 38 20 42 79 74 65 73 20 0D 07 4E 50 0D 07 0D 07 43 57 44 20 96 20 43 6F 6E change 8 Bytes ♪•NP♪•♪•CWD û Con 00010320 76 65 72 74 20 57 6F 72 64 20 74 6F 20 44 77 6F 72 64 20 0B 43 44 51 20 96 20 43 6F 6E 76 65 72 vert Word to Dword ♂CDQ û Conver 00010340 74 20 44 77 6F 72 64 20 74 6F 20 51 77 6F 72 64 0D 07 4E 50 0D 07 0D 07 44 41 41 20 96 20 44 65 t Dword to Qword♪•NP♪•♪•DAA û De 00010360 63 69 6D 61 6C 20 41 64 6A 75 73 74 20 41 4C 20 61 66 74 65 72 20 41 64 64 69 74 69 6F 6E 0D 07 cimal Adjust AL after Addition♪• 00010380 4E 50 0D 07 0D 07 44 41 53 20 96 20 44 65 63 69 6D 61 6C 20 41 64 6A 75 73 74 20 41 4C 20 61 66 NP♪•♪•DAS û Decimal Adjust AL af 000103A0 74 65 72 20 53 75 62 74 72 61 63 74 69 6F 6E 0D 07 4E 50 0D 07 0D 07 44 45 43 20 96 20 44 65 63 ter Subtraction♪•NP♪•♪•DEC û Dec 000103C0 72 65 6D 65 6E 74 20 62 79 20 31 0D 07 55 56 0D 07 0D 07 44 49 56 20 96 20 55 6E 73 69 67 6E 65 rement by 1♪•UV♪•♪•DIV û Unsigne 000103E0 64 20 44 69 76 69 64 65 0D 07 4E 50 0D 07 0D 07 45 4E 54 45 52 20 96 20 4D 61 6B 65 20 53 74 61 d Divide♪•NP♪•♪•ENTER û Make Sta 00010400 63 6B 20 46 72 61 6D 65 20 66 6F 72 20 50 72 6F 63 65 64 75 72 65 20 50 61 72 61 6D 65 74 65 72 ck Frame for Procedure Parameter 00010420 73 0D 07 4E 50 0D 07 0D 07 48 4C 54 20 96 20 48 61 6C 74 0D 07 0D 07 0D 07 0C 49 6E 74 65 67 65 s♪•NP♪•♪•HLT û Halt♪•♪•♪•♀Intege 00010440 72 20 49 6E 73 74 72 75 63 74 69 6F 6E 20 50 61 69 72 69 6E 67 20 28 43 6F 6E 74 69 6E 75 65 64 r Instruction Pairing (Continued 00010460 29 0D 0A 49 4E 53 54 52 55 43 54 49 4F 4E 09 46 4F 52 4D 41 54 0D 07 50 61 69 72 69 6E 67 0D 07 )♪◙INSTRUCTION○FORMAT♪•Pairing♪• 00010480 0D 07 49 44 49 56 20 96 20 53 69 67 6E 65 64 20 44 69 76 69 64 65 0D 07 4E 50 0D 07 0D 07 49 4D ♪•IDIV û Signed Divide♪•NP♪•♪•IM 000104A0 55 4C 20 96 20 53 69 67 6E 65 64 20 4D 75 6C 74 69 70 6C 79 0D 07 4E 50 0D 07 0D 07 49 4E 43 20 UL û Signed Multiply♪•NP♪•♪•INC 000104C0 96 20 49 6E 63 72 65 6D 65 6E 74 20 62 79 20 31 0D 07 55 56 0D 07 0D 07 49 4E 54 20 6E 20 96 20 û Increment by 1♪•UV♪•♪•INT n û 000104E0 49 6E 74 65 72 72 75 70 74 20 54 79 70 65 20 6E 20 0D 07 4E 50 0D 07 0D 07 49 4E 54 20 96 20 53 Interrupt Type n ♪•NP♪•♪•INT û S 00010500 69 6E 67 6C 65 2D 53 74 65 70 20 49 6E 74 65 72 72 75 70 74 20 33 0D 07 4E 50 0D 07 0D 07 49 4E ingle-Step Interrupt 3♪•NP♪•♪•IN 00010520 54 4F 20 96 20 49 6E 74 65 72 72 75 70 74 20 34 20 6F 6E 20 4F 76 65 72 66 6C 6F 77 0D 07 4E 50 TO û Interrupt 4 on Overflow♪•NP 00010540 0D 07 0D 07 49 4E 56 44 20 96 20 49 6E 76 61 6C 69 64 61 74 65 20 43 61 63 68 65 0D 07 4E 50 0D ♪•♪•INVD û Invalidate Cache♪•NP♪ 00010560 07 0D 07 49 4E 56 4C 50 47 20 96 20 49 6E 76 61 6C 69 64 61 74 65 20 54 4C 42 20 45 6E 74 72 79 •♪•INVLPG û Invalidate TLB Entry 00010580 0D 07 4E 50 0D 07 0D 07 49 52 45 54 2F 49 52 45 54 44 20 96 20 49 6E 74 65 72 72 75 70 74 20 52 ♪•NP♪•♪•IRET/IRETD û Interrupt R 000105A0 65 74 75 72 6E 0D 07 4E 50 0D 07 0D 07 4A 63 63 20 96 20 4A 75 6D 70 20 69 66 20 43 6F 6E 64 69 eturn♪•NP♪•♪•Jcc û Jump if Condi 000105C0 74 69 6F 6E 20 69 73 20 4D 65 74 0D 07 50 56 0D 07 0D 07 4A 43 58 5A 2F 4A 45 43 58 5A 20 96 20 tion is Met♪•PV♪•♪•JCXZ/JECXZ û 000105E0 4A 75 6D 70 20 6F 6E 20 43 58 2F 45 43 58 20 5A 65 72 6F 0D 07 4E 50 0D 07 0D 07 4A 4D 50 20 96 Jump on CX/ECX Zero♪•NP♪•♪•JMP û 00010600 20 55 6E 63 6F 6E 64 69 74 69 6F 6E 61 6C 20 4A 75 6D 70 20 28 74 6F 20 73 61 6D 65 20 73 65 67 Unconditional Jump (to same seg 00010620 6D 65 6E 74 29 0D 07 0D 07 0D 07 A0 A0 A0 73 68 6F 72 74 09 31 31 31 30 20 31 30 31 31 20 3A 20 ment)♪•♪•♪•áááshort○1110 1011 : 00010640 38 2D 62 69 74 20 64 69 73 70 6C 61 63 65 6D 65 6E 74 0D 07 50 56 0D 07 0D 07 A0 A0 A0 64 69 72 8-bit displacement♪•PV♪•♪•ááádir 00010660 65 63 74 09 31 31 31 30 20 31 30 30 31 20 3A 20 66 75 6C 6C 20 64 69 73 70 6C 61 63 65 6D 65 6E ect○1110 1001 : full displacemen 00010680 74 0D 07 50 56 0D 07 0D 07 A0 A0 A0 72 65 67 69 73 74 65 72 20 69 6E 64 69 72 65 63 74 09 31 31 t♪•PV♪•♪•áááregister indirect○11 000106A0 31 31 20 31 31 31 31 20 3A 20 31 31 20 31 30 30 20 72 65 67 0D 07 4E 50 0D 07 0D 07 A0 A0 A0 6D 11 1111 : 11 100 reg♪•NP♪•♪•ááám 000106C0 65 6D 6F 72 79 20 69 6E 64 69 72 65 63 74 09 31 31 31 31 20 31 31 31 31 20 3A 20 6D 6F 64 20 31 emory indirect○1111 1111 : mod 1 000106E0 30 30 20 72 2F 6D 0D 07 4E 50 0D 07 0D 07 4A 4D 50 20 96 20 55 6E 63 6F 6E 64 69 74 69 6F 6E 61 00 r/m♪•NP♪•♪•JMP û Unconditiona 00010700 6C 20 4A 75 6D 70 20 28 74 6F 20 6F 74 68 65 72 20 73 65 67 6D 65 6E 74 29 0D 07 4E 50 0D 07 0D l Jump (to other segment)♪•NP♪•♪ 00010720 07 4C 41 48 46 20 96 20 4C 6F 61 64 20 46 6C 61 67 73 20 69 6E 74 6F 20 41 48 20 52 65 67 69 73 •LAHF û Load Flags into AH Regis 00010740 74 65 72 0D 07 4E 50 0D 07 0D 07 4C 41 52 20 96 20 4C 6F 61 64 20 41 63 63 65 73 73 20 52 69 67 ter♪•NP♪•♪•LAR û Load Access Rig 00010760 68 74 73 20 42 79 74 65 0D 07 4E 50 0D 07 0D 07 4C 44 53 20 96 20 4C 6F 61 64 20 50 6F 69 6E 74 hts Byte♪•NP♪•♪•LDS û Load Point 00010780 65 72 20 74 6F 20 44 53 0D 07 4E 50 0D 07 0D 07 4C 45 41 20 96 20 4C 6F 61 64 20 45 66 66 65 63 er to DS♪•NP♪•♪•LEA û Load Effec 000107A0 74 69 76 65 20 41 64 64 72 65 73 73 0D 07 55 56 0D 07 0D 07 4C 45 41 56 45 20 96 20 48 69 67 68 tive Address♪•UV♪•♪•LEAVE û High 000107C0 20 4C 65 76 65 6C 20 50 72 6F 63 65 64 75 72 65 20 45 78 69 74 0D 07 4E 50 0D 07 0D 07 4C 45 53 Level Procedure Exit♪•NP♪•♪•LES 000107E0 20 96 20 4C 6F 61 64 20 50 6F 69 6E 74 65 72 20 74 6F 20 45 53 20 0D 07 4E 50 0D 07 0D 07 4C 46 û Load Pointer to ES ♪•NP♪•♪•LF 00010800 53 20 96 20 4C 6F 61 64 20 50 6F 69 6E 74 65 72 20 74 6F 20 46 53 20 0D 07 4E 50 0D 07 0D 07 4C S û Load Pointer to FS ♪•NP♪•♪•L 00010820 47 44 54 20 96 20 4C 6F 61 64 20 47 6C 6F 62 61 6C 20 44 65 73 63 72 69 70 74 6F 72 20 54 61 62 GDT û Load Global Descriptor Tab 00010840 6C 65 20 52 65 67 69 73 74 65 72 0D 07 4E 50 0D 07 0D 07 4C 47 53 20 96 20 4C 6F 61 64 20 50 6F le Register♪•NP♪•♪•LGS û Load Po 00010860 69 6E 74 65 72 20 74 6F 20 47 53 20 0D 07 4E 50 0D 07 0D 07 4C 49 44 54 20 96 20 4C 6F 61 64 20 inter to GS ♪•NP♪•♪•LIDT û Load 00010880 49 6E 74 65 72 72 75 70 74 20 44 65 73 63 72 69 70 74 6F 72 20 54 61 62 6C 65 20 52 65 67 69 73 Interrupt Descriptor Table Regis 000108A0 74 65 72 0D 07 4E 50 0D 07 0D 07 4C 4C 44 54 20 96 20 4C 6F 61 64 20 4C 6F 63 61 6C 20 44 65 73 ter♪•NP♪•♪•LLDT û Load Local Des 000108C0 63 72 69 70 74 6F 72 20 54 61 62 6C 65 20 52 65 67 69 73 74 65 72 0D 07 4E 50 0D 07 0D 07 4C 4D criptor Table Register♪•NP♪•♪•LM 000108E0 53 57 20 96 20 4C 6F 61 64 20 4D 61 63 68 69 6E 65 20 53 74 61 74 75 73 20 57 6F 72 64 0D 07 4E SW û Load Machine Status Word♪•N 00010900 50 0D 07 0D 07 4C 4F 43 4B 20 96 20 41 73 73 65 72 74 20 4C 4F 43 4B 23 20 53 69 67 6E 61 6C 20 P♪•♪•LOCK û Assert LOCK# Signal 00010920 50 72 65 66 69 78 0D 07 0D 07 0D 07 4C 4F 44 53 2F 4C 4F 44 53 42 2F 4C 4F 44 53 57 2F 4C 4F 44 Prefix♪•♪•♪•LODS/LODSB/LODSW/LOD 00010940 53 44 20 96 20 4C 6F 61 64 20 53 74 72 69 6E 67 20 4F 70 65 72 61 6E 64 0D 07 4E 50 0D 07 0D 07 SD û Load String Operand♪•NP♪•♪• 00010960 4C 4F 4F 50 20 96 20 4C 6F 6F 70 20 43 6F 75 6E 74 20 0D 07 4E 50 0D 07 0D 07 4C 4F 4F 50 5A 2F LOOP û Loop Count ♪•NP♪•♪•LOOPZ/ 00010980 4C 4F 4F 50 45 20 96 20 4C 6F 6F 70 20 43 6F 75 6E 74 20 77 68 69 6C 65 20 5A 65 72 6F 2F 45 71 LOOPE û Loop Count while Zero/Eq 000109A0 75 61 6C 0D 07 4E 50 0D 07 0D 07 4C 4F 4F 50 4E 5A 2F 4C 4F 4F 50 4E 45 20 96 20 4C 6F 6F 70 20 ual♪•NP♪•♪•LOOPNZ/LOOPNE û Loop 000109C0 43 6F 75 6E 74 20 77 68 69 6C 65 20 6E 6F 74 20 5A 65 72 6F 2F 45 71 75 61 6C 0D 07 4E 50 0D 07 Count while not Zero/Equal♪•NP♪• 000109E0 0D 07 4C 53 4C 20 96 20 4C 6F 61 64 20 53 65 67 6D 65 6E 74 20 4C 69 6D 69 74 0D 07 4E 50 0D 07 ♪•LSL û Load Segment Limit♪•NP♪• 00010A00 0D 07 4C 53 53 20 96 20 4C 6F 61 64 20 50 6F 69 6E 74 65 72 20 74 6F 20 53 53 09 30 30 30 30 20 ♪•LSS û Load Pointer to SS○0000 00010A20 31 31 31 31 20 3A 20 31 30 31 31 20 30 30 31 30 20 3A 20 6D 6F 64 20 72 65 67 20 72 2F 6D 0D 07 1111 : 1011 0010 : mod reg r/m♪• 00010A40 4E 50 0D 07 0D 07 4C 54 52 20 96 20 4C 6F 61 64 20 54 61 73 6B 20 52 65 67 69 73 74 65 72 0D 07 NP♪•♪•LTR û Load Task Register♪• 00010A60 4E 50 0D 07 0D 07 4D 4F 56 20 96 20 4D 6F 76 65 20 44 61 74 61 0D 07 55 56 0D 07 0D 07 4D 4F 56 NP♪•♪•MOV û Move Data♪•UV♪•♪•MOV 00010A80 20 96 20 4D 6F 76 65 20 74 6F 2F 66 72 6F 6D 20 43 6F 6E 74 72 6F 6C 20 52 65 67 69 73 74 65 72 û Move to/from Control Register 00010AA0 73 0D 07 4E 50 0D 07 0D 07 4D 4F 56 20 96 20 4D 6F 76 65 20 74 6F 2F 66 72 6F 6D 20 44 65 62 75 s♪•NP♪•♪•MOV û Move to/from Debu 00010AC0 67 20 52 65 67 69 73 74 65 72 73 0D 07 4E 50 0D 07 0D 07 0C 49 6E 74 65 67 65 72 20 49 6E 73 74 g Registers♪•NP♪•♪•♀Integer Inst 00010AE0 72 75 63 74 69 6F 6E 20 50 61 69 72 69 6E 67 20 28 43 6F 6E 74 69 6E 75 65 64 29 0D 0A 49 4E 53 ruction Pairing (Continued)♪◙INS 00010B00 54 52 55 43 54 49 4F 4E 09 46 4F 52 4D 41 54 0D 07 50 61 69 72 69 6E 67 0D 07 0D 07 4D 4F 56 20 TRUCTION○FORMAT♪•Pairing♪•♪•MOV 00010B20 96 20 4D 6F 76 65 20 74 6F 2F 66 72 6F 6D 20 53 65 67 6D 65 6E 74 20 52 65 67 69 73 74 65 72 73 û Move to/from Segment Registers 00010B40 0D 07 4E 50 0D 07 0D 07 4D 4F 56 53 2F 4D 4F 56 53 42 2F 4D 4F 56 53 57 2F 4D 4F 56 53 44 20 96 ♪•NP♪•♪•MOVS/MOVSB/MOVSW/MOVSD û 00010B60 20 4D 6F 76 65 20 44 61 74 61 20 66 72 6F 6D 20 53 74 72 69 6E 67 20 74 6F 20 53 74 72 69 6E 67 Move Data from String to String 00010B80 0D 07 4E 50 0D 07 0D 07 4D 4F 56 53 58 20 96 20 4D 6F 76 65 20 77 69 74 68 20 53 69 67 6E 2D 45 ♪•NP♪•♪•MOVSX û Move with Sign-E 00010BA0 78 74 65 6E 64 0D 07 4E 50 0D 07 0D 07 4D 4F 56 5A 58 20 96 20 4D 6F 76 65 20 77 69 74 68 20 5A xtend♪•NP♪•♪•MOVZX û Move with Z 00010BC0 65 72 6F 2D 45 78 74 65 6E 64 0D 07 4E 50 0D 07 0D 07 4D 55 4C 20 96 20 55 6E 73 69 67 6E 65 64 ero-Extend♪•NP♪•♪•MUL û Unsigned 00010BE0 20 4D 75 6C 74 69 70 6C 69 63 61 74 69 6F 6E 20 6F 66 20 41 4C 2C 20 41 58 20 6F 72 20 45 41 58 Multiplication of AL, AX or EAX 00010C00 0D 07 4E 50 0D 07 0D 07 4E 45 47 20 96 20 54 77 6F 27 73 20 43 6F 6D 70 6C 65 6D 65 6E 74 20 4E ♪•NP♪•♪•NEG û Two's Complement N 00010C20 65 67 61 74 69 6F 6E 0D 07 4E 50 0D 07 0D 07 4E 4F 50 20 96 20 4E 6F 20 4F 70 65 72 61 74 69 6F egation♪•NP♪•♪•NOP û No Operatio 00010C40 6E 09 31 30 30 31 20 30 30 30 30 0D 07 55 56 0D 07 0D 07 4E 4F 54 20 96 20 4F 6E 65 27 73 20 43 n○1001 0000♪•UV♪•♪•NOT û One's C 00010C60 6F 6D 70 6C 65 6D 65 6E 74 20 4E 65 67 61 74 69 6F 6E 0D 07 4E 50 0D 07 0D 07 4F 52 20 96 20 4C omplement Negation♪•NP♪•♪•OR û L 00010C80 6F 67 69 63 61 6C 20 49 6E 63 6C 75 73 69 76 65 20 4F 52 0D 07 55 56 0D 07 0D 07 50 4F 50 20 96 ogical Inclusive OR♪•UV♪•♪•POP û 00010CA0 20 50 6F 70 20 61 20 57 6F 72 64 20 66 72 6F 6D 20 74 68 65 20 53 74 61 63 6B 0D 07 0D 07 0D 07 Pop a Word from the Stack♪•♪•♪• 00010CC0 A0 A0 A0 72 65 67 09 31 30 30 30 20 31 31 31 31 20 3A 20 31 31 20 30 30 30 20 72 65 67 0D 07 55 áááreg○1000 1111 : 11 000 reg♪•U 00010CE0 56 0D 07 0D 07 A0 A0 A0 A0 A0 A0 6F 72 09 30 31 30 31 20 31 20 72 65 67 0D 07 55 56 0D 07 0D 07 V♪•♪•ááááááor○0101 1 reg♪•UV♪•♪• 00010D00 A0 A0 A0 6D 65 6D 6F 72 79 09 31 30 30 30 20 31 31 31 31 20 3A 20 6D 6F 64 20 30 30 30 20 72 2F ááámemory○1000 1111 : mod 000 r/ 00010D20 6D 0D 07 4E 50 0D 07 0D 07 50 4F 50 20 96 20 50 6F 70 20 61 20 53 65 67 6D 65 6E 74 20 52 65 67 m♪•NP♪•♪•POP û Pop a Segment Reg 00010D40 69 73 74 65 72 20 66 72 6F 6D 20 74 68 65 20 53 74 61 63 6B 0D 07 4E 50 0D 07 0D 07 50 4F 50 41 ister from the Stack♪•NP♪•♪•POPA 00010D60 2F 50 4F 50 41 44 20 96 20 50 6F 70 20 41 6C 6C 20 47 65 6E 65 72 61 6C 20 52 65 67 69 73 74 65 /POPAD û Pop All General Registe 00010D80 72 73 0D 07 4E 50 0D 07 0D 07 50 4F 50 46 2F 50 4F 50 46 44 20 96 20 50 6F 70 20 53 74 61 63 6B rs♪•NP♪•♪•POPF/POPFD û Pop Stack 00010DA0 20 69 6E 74 6F 20 46 4C 41 47 53 20 6F 72 20 45 46 4C 41 47 53 20 52 65 67 69 73 74 65 72 0D 07 into FLAGS or EFLAGS Register♪• 00010DC0 4E 50 0D 07 0D 07 50 55 53 48 20 96 20 50 75 73 68 20 4F 70 65 72 61 6E 64 20 6F 6E 74 6F 20 74 NP♪•♪•PUSH û Push Operand onto t 00010DE0 68 65 20 53 74 61 63 6B 0D 07 0D 07 0D 07 A0 A0 A0 72 65 67 09 31 31 31 31 20 31 31 31 31 20 3A he Stack♪•♪•♪•áááreg○1111 1111 : 00010E00 20 31 31 20 31 31 30 20 72 65 67 0D 07 55 56 0D 07 0D 07 A0 A0 A0 A0 A0 A0 6F 72 09 30 31 30 31 11 110 reg♪•UV♪•♪•ááááááor○0101 00010E20 20 30 20 72 65 67 0D 07 55 56 0D 07 0D 07 A0 A0 A0 6D 65 6D 6F 72 79 09 31 31 31 31 20 31 31 31 0 reg♪•UV♪•♪•ááámemory○1111 111 00010E40 31 20 3A 20 6D 6F 64 20 31 31 30 20 72 2F 6D 0D 07 4E 50 0D 07 0D 07 A0 A0 A0 69 6D 6D 65 64 69 1 : mod 110 r/m♪•NP♪•♪•áááimmedi 00010E60 61 74 65 09 30 31 31 30 20 31 30 73 30 20 3A 20 69 6D 6D 65 64 69 61 74 65 20 64 61 74 61 0D 07 ate○0110 10s0 : immediate data♪• 00010E80 55 56 0D 07 0D 07 50 55 53 48 20 96 20 50 75 73 68 20 53 65 67 6D 65 6E 74 20 52 65 67 69 73 74 UV♪•♪•PUSH û Push Segment Regist 00010EA0 65 72 20 6F 6E 74 6F 20 74 68 65 20 53 74 61 63 6B 0D 07 4E 50 0D 07 0D 07 50 55 53 48 41 2F 50 er onto the Stack♪•NP♪•♪•PUSHA/P 00010EC0 55 53 48 41 44 20 96 20 50 75 73 68 20 41 6C 6C 20 47 65 6E 65 72 61 6C 20 52 65 67 69 73 74 65 USHAD û Push All General Registe 00010EE0 72 73 0D 07 4E 50 0D 07 0D 07 50 55 53 48 46 2F 50 55 53 48 46 44 20 96 20 50 75 73 68 20 46 6C rs♪•NP♪•♪•PUSHF/PUSHFD û Push Fl 00010F00 61 67 73 20 52 65 67 69 73 74 65 72 20 6F 6E 74 6F 20 74 68 65 20 53 74 61 63 6B 0D 07 4E 50 0D ags Register onto the Stack♪•NP♪ 00010F20 07 0D 07 52 43 4C 20 96 20 52 6F 74 61 74 65 20 74 68 72 75 20 43 61 72 72 79 20 4C 65 66 74 0D •♪•RCL û Rotate thru Carry Left♪ 00010F40 07 0D 07 0D 07 A0 A0 A0 72 65 67 20 62 79 20 31 09 31 31 30 31 20 30 30 30 77 20 3A 20 31 31 20 •♪•♪•áááreg by 1○1101 000w : 11 00010F60 30 31 30 20 72 65 67 0D 07 50 55 0D 07 0D 07 A0 A0 A0 6D 65 6D 6F 72 79 20 62 79 20 31 09 31 31 010 reg♪•PU♪•♪•ááámemory by 1○11 00010F80 30 31 20 30 30 30 77 20 3A 20 6D 6F 64 20 30 31 30 20 72 2F 6D 0D 07 50 55 0D 07 0D 07 A0 A0 A0 01 000w : mod 010 r/m♪•PU♪•♪•ááá 00010FA0 72 65 67 20 62 79 20 43 4C 09 31 31 30 31 20 30 30 31 77 20 3A 20 31 31 20 30 31 30 20 72 65 67 reg by CL○1101 001w : 11 010 reg 00010FC0 0D 07 4E 50 0D 07 0D 07 A0 A0 A0 6D 65 6D 6F 72 79 20 62 79 20 43 4C 09 31 31 30 31 20 30 30 31 ♪•NP♪•♪•ááámemory by CL○1101 001 00010FE0 77 20 3A 20 6D 6F 64 20 30 31 30 20 72 2F 6D 0D 07 4E 50 0D 07 0D 07 A0 A0 A0 72 65 67 20 62 79 w : mod 010 r/m♪•NP♪•♪•áááreg by 00011000 20 69 6D 6D 65 64 69 61 74 65 20 63 6F 75 6E 74 09 31 31 30 30 20 30 30 30 77 20 3A 20 31 31 20 immediate count○1100 000w : 11 00011020 30 31 30 20 72 65 67 20 3A 20 69 6D 6D 38 20 64 61 74 61 0D 07 50 55 0D 07 0D 07 A0 A0 A0 6D 65 010 reg : imm8 data♪•PU♪•♪•áááme 00011040 6D 6F 72 79 20 62 79 20 69 6D 6D 65 64 69 61 74 65 20 63 6F 75 6E 74 09 31 31 30 30 20 30 30 30 mory by immediate count○1100 000 00011060 77 20 3A 20 6D 6F 64 20 30 31 30 20 72 2F 6D 20 3A 20 69 6D 6D 38 20 64 61 74 61 0D 07 50 55 0D w : mod 010 r/m : imm8 data♪•PU♪ 00011080 07 0D 07 52 43 52 20 96 20 52 6F 74 61 74 65 20 74 68 72 75 20 43 61 72 72 79 20 52 69 67 68 74 •♪•RCR û Rotate thru Carry Right 000110A0 0D 07 0D 07 0D 07 A0 A0 A0 72 65 67 20 62 79 20 31 09 31 31 30 31 20 30 30 30 77 20 3A 20 31 31 ♪•♪•♪•áááreg by 1○1101 000w : 11 000110C0 20 30 31 31 20 72 65 67 0D 07 50 55 0D 07 0D 07 A0 A0 A0 6D 65 6D 6F 72 79 20 62 79 20 31 09 31 011 reg♪•PU♪•♪•ááámemory by 1○1 000110E0 31 30 31 20 30 30 30 77 20 3A 20 6D 6F 64 20 30 31 31 20 72 2F 6D 0D 07 50 55 0D 07 0D 07 A0 A0 101 000w : mod 011 r/m♪•PU♪•♪•áá 00011100 A0 72 65 67 20 62 79 20 43 4C 09 31 31 30 31 20 30 30 31 77 20 3A 20 31 31 20 30 31 31 20 72 65 áreg by CL○1101 001w : 11 011 re 00011120 67 0D 07 4E 50 0D 07 0D 07 A0 A0 A0 6D 65 6D 6F 72 79 20 62 79 20 43 4C 09 31 31 30 31 20 30 30 g♪•NP♪•♪•ááámemory by CL○1101 00 00011140 31 77 20 3A 20 6D 6F 64 20 30 31 31 20 72 2F 6D 0D 07 4E 50 0D 07 0D 07 A0 A0 A0 72 65 67 20 62 1w : mod 011 r/m♪•NP♪•♪•áááreg b 00011160 79 20 69 6D 6D 65 64 69 61 74 65 20 63 6F 75 6E 74 09 31 31 30 30 20 30 30 30 77 20 3A 20 31 31 y immediate count○1100 000w : 11 00011180 20 30 31 31 20 72 65 67 20 3A 20 69 6D 6D 38 20 64 61 74 61 0D 07 50 55 0D 07 0D 07 A0 A0 A0 6D 011 reg : imm8 data♪•PU♪•♪•ááám 000111A0 65 6D 6F 72 79 20 62 79 20 69 6D 6D 65 64 69 61 74 65 20 63 6F 75 6E 74 09 31 31 30 30 20 30 30 emory by immediate count○1100 00 000111C0 30 77 20 3A 20 6D 6F 64 20 30 31 31 20 72 2F 6D 20 3A 20 69 6D 6D 38 20 64 61 74 61 0D 07 50 55 0w : mod 011 r/m : imm8 data♪•PU 000111E0 0D 07 0D 07 52 44 4D 53 52 20 96 20 52 65 61 64 20 66 72 6F 6D 20 4D 6F 64 65 6C 2D 53 70 65 63 ♪•♪•RDMSR û Read from Model-Spec 00011200 69 66 69 63 20 52 65 67 69 73 74 65 72 0D 07 4E 50 0D 07 0D 07 52 45 50 20 4C 4F 44 53 20 96 20 ific Register♪•NP♪•♪•REP LODS û 00011220 4C 6F 61 64 20 53 74 72 69 6E 67 0D 07 4E 50 0D 07 0D 07 0C 49 6E 74 65 67 65 72 20 49 6E 73 74 Load String♪•NP♪•♪•♀Integer Inst 00011240 72 75 63 74 69 6F 6E 20 50 61 69 72 69 6E 67 20 28 43 6F 6E 74 69 6E 75 65 64 29 0D 0A 49 4E 53 ruction Pairing (Continued)♪◙INS 00011260 54 52 55 43 54 49 4F 4E 09 46 4F 52 4D 41 54 0D 07 50 61 69 72 69 6E 67 0D 07 0D 07 52 45 50 20 TRUCTION○FORMAT♪•Pairing♪•♪•REP 00011280 4D 4F 56 53 20 96 20 4D 6F 76 65 20 53 74 72 69 6E 67 0D 07 4E 50 0D 07 0D 07 52 45 50 20 53 54 MOVS û Move String♪•NP♪•♪•REP ST 000112A0 4F 53 20 96 20 53 74 6F 72 65 20 53 74 72 69 6E 67 0D 07 4E 50 0D 07 0D 07 52 45 50 45 20 43 4D OS û Store String♪•NP♪•♪•REPE CM 000112C0 50 53 20 96 20 43 6F 6D 70 61 72 65 20 53 74 72 69 6E 67 20 28 46 69 6E 64 20 4E 6F 6E 2D 4D 61 PS û Compare String (Find Non-Ma 000112E0 74 63 68 29 0D 07 4E 50 0D 07 0D 07 52 45 50 45 20 53 43 41 53 20 96 20 53 63 61 6E 20 53 74 72 tch)♪•NP♪•♪•REPE SCAS û Scan Str 00011300 69 6E 67 20 28 46 69 6E 64 20 4E 6F 6E 2D 41 4C 2F 41 58 2F 45 41 58 29 0D 07 4E 50 0D 07 0D 07 ing (Find Non-AL/AX/EAX)♪•NP♪•♪• 00011320 52 45 50 4E 45 20 43 4D 50 53 20 96 20 43 6F 6D 70 61 72 65 20 53 74 72 69 6E 67 20 28 46 69 6E REPNE CMPS û Compare String (Fin 00011340 64 20 4D 61 74 63 68 29 0D 07 4E 50 0D 07 0D 07 52 45 50 4E 45 20 53 43 41 53 20 96 20 53 63 61 d Match)♪•NP♪•♪•REPNE SCAS û Sca 00011360 6E 20 53 74 72 69 6E 67 20 28 46 69 6E 64 20 41 4C 2F 41 58 2F 45 41 58 29 0D 07 4E 50 0D 07 0D n String (Find AL/AX/EAX)♪•NP♪•♪ 00011380 07 52 45 54 20 96 20 52 65 74 75 72 6E 20 66 72 6F 6D 20 50 72 6F 63 65 64 75 72 65 20 28 74 6F •RET û Return from Procedure (to 000113A0 20 73 61 6D 65 20 73 65 67 6D 65 6E 74 29 0D 07 4E 50 0D 07 0D 07 52 45 54 20 96 20 52 65 74 75 same segment)♪•NP♪•♪•RET û Retu 000113C0 72 6E 20 66 72 6F 6D 20 50 72 6F 63 65 64 75 72 65 20 28 74 6F 20 6F 74 68 65 72 20 73 65 67 6D rn from Procedure (to other segm 000113E0 65 6E 74 29 0D 07 4E 50 0D 07 0D 07 52 4F 4C 20 96 20 52 6F 74 61 74 65 20 28 6E 6F 74 20 74 68 ent)♪•NP♪•♪•ROL û Rotate (not th 00011400 72 75 20 43 61 72 72 79 29 20 4C 65 66 74 0D 07 0D 07 0D 07 A0 A0 A0 72 65 67 20 62 79 20 31 09 ru Carry) Left♪•♪•♪•áááreg by 1○ 00011420 31 31 30 31 20 30 30 30 77 20 3A 20 31 31 20 30 30 30 20 72 65 67 0D 07 50 55 0D 07 0D 07 A0 A0 1101 000w : 11 000 reg♪•PU♪•♪•áá 00011440 A0 6D 65 6D 6F 72 79 20 62 79 20 31 09 31 31 30 31 20 30 30 30 77 20 3A 20 6D 6F 64 20 30 30 30 ámemory by 1○1101 000w : mod 000 00011460 20 72 2F 6D 0D 07 50 55 0D 07 0D 07 A0 A0 A0 72 65 67 20 62 79 20 43 4C 09 31 31 30 31 20 30 30 r/m♪•PU♪•♪•áááreg by CL○1101 00 00011480 31 77 20 3A 20 31 31 20 30 30 30 20 72 65 67 0D 07 4E 50 0D 07 0D 07 A0 A0 A0 6D 65 6D 6F 72 79 1w : 11 000 reg♪•NP♪•♪•ááámemory 000114A0 20 62 79 20 43 4C 09 31 31 30 31 20 30 30 31 77 20 3A 20 6D 6F 64 20 30 30 30 20 72 2F 6D 0D 07 by CL○1101 001w : mod 000 r/m♪• 000114C0 4E 50 0D 07 0D 07 A0 A0 A0 72 65 67 20 62 79 20 69 6D 6D 65 64 69 61 74 65 20 63 6F 75 6E 74 09 NP♪•♪•áááreg by immediate count○ 000114E0 31 31 30 30 20 30 30 30 77 20 3A 20 31 31 20 30 30 30 20 72 65 67 20 3A 20 69 6D 6D 38 20 64 61 1100 000w : 11 000 reg : imm8 da 00011500 74 61 0D 07 50 55 0D 07 0D 07 A0 A0 A0 6D 65 6D 6F 72 79 20 62 79 20 69 6D 6D 65 64 69 61 74 65 ta♪•PU♪•♪•ááámemory by immediate 00011520 20 63 6F 75 6E 74 09 31 31 30 30 20 30 30 30 77 20 3A 20 6D 6F 64 20 30 30 30 20 72 2F 6D 20 3A count○1100 000w : mod 000 r/m : 00011540 20 69 6D 6D 38 20 64 61 74 61 0D 07 50 55 0D 07 0D 07 52 4F 52 20 96 20 52 6F 74 61 74 65 20 28 imm8 data♪•PU♪•♪•ROR û Rotate ( 00011560 6E 6F 74 20 74 68 72 75 20 43 61 72 72 79 29 20 52 69 67 68 74 0D 07 0D 07 0D 07 A0 A0 A0 72 65 not thru Carry) Right♪•♪•♪•áááre 00011580 67 20 62 79 20 31 09 31 31 30 31 20 30 30 30 77 20 3A 20 31 31 20 30 30 31 20 72 65 67 0D 07 50 g by 1○1101 000w : 11 001 reg♪•P 000115A0 55 0D 07 0D 07 A0 A0 A0 6D 65 6D 6F 72 79 20 62 79 20 31 09 31 31 30 31 20 30 30 30 77 20 3A 20 U♪•♪•ááámemory by 1○1101 000w : 000115C0 6D 6F 64 20 30 30 31 20 72 2F 6D 0D 07 50 55 0D 07 0D 07 A0 A0 A0 72 65 67 20 62 79 20 43 4C 09 mod 001 r/m♪•PU♪•♪•áááreg by CL○ 000115E0 31 31 30 31 20 30 30 31 77 20 3A 20 31 31 20 30 30 31 20 72 65 67 0D 07 4E 50 0D 07 0D 07 A0 A0 1101 001w : 11 001 reg♪•NP♪•♪•áá 00011600 A0 6D 65 6D 6F 72 79 20 62 79 20 43 4C 09 31 31 30 31 20 30 30 31 77 20 3A 20 6D 6F 64 20 30 30 ámemory by CL○1101 001w : mod 00 00011620 31 20 72 2F 6D 0D 07 4E 50 0D 07 0D 07 A0 A0 A0 72 65 67 20 62 79 20 69 6D 6D 65 64 69 61 74 65 1 r/m♪•NP♪•♪•áááreg by immediate 00011640 20 63 6F 75 6E 74 09 31 31 30 30 20 30 30 30 77 20 3A 20 31 31 20 30 30 31 20 72 65 67 20 3A 20 count○1100 000w : 11 001 reg : 00011660 69 6D 6D 38 20 64 61 74 61 0D 07 50 55 0D 07 0D 07 A0 A0 A0 6D 65 6D 6F 72 79 20 62 79 20 69 6D imm8 data♪•PU♪•♪•ááámemory by im 00011680 6D 65 64 69 61 74 65 20 63 6F 75 6E 74 09 31 31 30 30 20 30 30 30 77 20 3A 20 6D 6F 64 20 30 30 mediate count○1100 000w : mod 00 000116A0 31 20 72 2F 6D 20 3A 20 69 6D 6D 38 20 64 61 74 61 0D 07 50 55 0D 07 0D 07 52 53 4D 20 96 20 52 1 r/m : imm8 data♪•PU♪•♪•RSM û R 000116C0 65 73 75 6D 65 20 66 72 6F 6D 20 53 79 73 74 65 6D 20 20 4D 61 6E 61 67 65 6D 65 6E 74 20 4D 6F esume from System Management Mo 000116E0 64 65 0D 07 4E 50 0D 07 0D 07 53 41 48 46 20 96 20 53 74 6F 72 65 20 41 48 20 69 6E 74 6F 20 46 de♪•NP♪•♪•SAHF û Store AH into F 00011700 6C 61 67 73 0D 07 4E 50 0D 07 0D 07 53 41 4C 20 96 20 53 68 69 66 74 20 41 72 69 74 68 6D 65 74 lags♪•NP♪•♪•SAL û Shift Arithmet 00011720 69 63 20 4C 65 66 74 09 73 61 6D 65 20 69 6E 73 74 72 75 63 74 69 6F 6E 20 61 73 20 53 48 4C 0D ic Left○same instruction as SHL♪ 00011740 07 0D 07 0D 07 53 41 52 20 96 20 53 68 69 66 74 20 41 72 69 74 68 6D 65 74 69 63 20 52 69 67 68 •♪•♪•SAR û Shift Arithmetic Righ 00011760 74 0D 07 0D 07 0D 07 A0 A0 A0 72 65 67 20 62 79 20 31 09 31 31 30 31 20 30 30 30 77 20 3A 20 31 t♪•♪•♪•áááreg by 1○1101 000w : 1 00011780 31 20 31 31 31 20 72 65 67 0D 07 50 55 0D 07 0D 07 A0 A0 A0 6D 65 6D 6F 72 79 20 62 79 20 31 09 1 111 reg♪•PU♪•♪•ááámemory by 1○ 000117A0 31 31 30 31 20 30 30 30 77 20 3A 20 6D 6F 64 20 31 31 31 20 72 2F 6D 0D 07 50 55 0D 07 0D 07 A0 1101 000w : mod 111 r/m♪•PU♪•♪•á 000117C0 A0 A0 72 65 67 20 62 79 20 43 4C 09 31 31 30 31 20 30 30 31 77 20 3A 20 31 31 20 31 31 31 20 72 ááreg by CL○1101 001w : 11 111 r 000117E0 65 67 0D 07 4E 50 0D 07 0D 07 A0 A0 A0 6D 65 6D 6F 72 79 20 62 79 20 43 4C 09 31 31 30 31 20 30 eg♪•NP♪•♪•ááámemory by CL○1101 0 00011800 30 31 77 20 3A 20 6D 6F 64 20 31 31 31 20 72 2F 6D 0D 07 4E 50 0D 07 0D 07 A0 A0 A0 72 65 67 20 01w : mod 111 r/m♪•NP♪•♪•áááreg 00011820 62 79 20 69 6D 6D 65 64 69 61 74 65 20 63 6F 75 6E 74 09 31 31 30 30 20 30 30 30 77 20 3A 20 31 by immediate count○1100 000w : 1 00011840 31 20 31 31 31 20 72 65 67 20 3A 20 69 6D 6D 38 20 64 61 74 61 0D 07 50 55 0D 07 0D 07 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20 69 6D 6D 65 64 69 61 74 65 20 64 61 74 61 0D 07 4E 50 mod 000 r/m : immediate data♪•NP 00012180 0D 07 0D 07 0C 49 6E 74 65 67 65 72 20 49 6E 73 74 72 75 63 74 69 6F 6E 20 50 61 69 72 69 6E 67 ♪•♪•♀Integer Instruction Pairing 000121A0 20 28 43 6F 6E 74 69 6E 75 65 64 29 0D 0A 49 4E 53 54 52 55 43 54 49 4F 4E 09 46 4F 52 4D 41 54 (Continued)♪◙INSTRUCTION○FORMAT 000121C0 0D 07 50 61 69 72 69 6E 67 0D 07 0D 07 56 45 52 52 20 96 20 56 65 72 69 66 79 20 61 20 53 65 67 ♪•Pairing♪•♪•VERR û Verify a Seg 000121E0 6D 65 6E 74 20 66 6F 72 20 52 65 61 64 69 6E 67 20 0D 07 4E 50 0D 07 0D 07 56 45 52 57 20 96 20 ment for Reading ♪•NP♪•♪•VERW û 00012200 56 65 72 69 66 79 20 61 20 53 65 67 6D 65 6E 74 20 66 6F 72 20 57 72 69 74 69 6E 67 0D 07 4E 50 Verify a Segment for Writing♪•NP 00012220 0D 07 0D 07 57 41 49 54 20 96 20 57 61 69 74 09 31 30 30 31 20 31 30 31 31 0D 07 4E 50 0D 07 0D ♪•♪•WAIT û Wait○1001 1011♪•NP♪•♪ 00012240 07 57 42 49 4E 56 44 20 96 20 57 72 69 74 65 2D 42 61 63 6B 20 61 6E 64 20 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Logical Exclusive 00012340 4F 52 0D 07 55 56 0D 07 0D 07 0C 46 6C 6F 61 74 69 6E 67 2D 50 6F 69 6E 74 20 49 6E 73 74 72 75 OR♪•UV♪•♪•♀Floating-Point Instru 00012360 63 74 69 6F 6E 20 50 61 69 72 69 6E 67 0D 0A 49 4E 53 54 52 55 43 54 49 4F 4E 09 46 4F 52 4D 41 ction Pairing♪◙INSTRUCTION○FORMA 00012380 54 0D 07 50 61 69 72 69 6E 67 0D 07 0D 07 46 32 58 4D 31 20 96 20 43 6F 6D 70 75 74 65 20 32 53 T♪•Pairing♪•♪•F2XM1 û Compute 2S 000123A0 54 28 30 29 20 96 20 31 0D 07 4E 50 0D 07 0D 07 46 41 42 53 20 96 20 41 62 73 6F 6C 75 74 65 20 T(0) û 1♪•NP♪•♪•FABS û Absolute 000123C0 56 61 6C 75 65 0D 07 46 58 0D 07 0D 07 46 41 44 44 20 96 20 41 64 64 0D 07 46 58 0D 07 0D 07 46 Value♪•FX♪•♪•FADD û Add♪•FX♪•♪•F 000123E0 41 44 44 50 20 96 20 41 64 64 20 61 6E 64 20 50 6F 70 0D 07 46 58 0D 07 0D 07 46 42 4C 44 20 96 ADDP û Add and Pop♪•FX♪•♪•FBLD û 00012400 20 4C 6F 61 64 20 42 69 6E 61 72 79 20 43 6F 64 65 64 20 44 65 63 69 6D 61 6C 0D 07 4E 50 0D 07 Load Binary Coded Decimal♪•NP♪• 00012420 0D 07 46 42 53 54 50 20 96 20 53 74 6F 72 65 20 42 69 6E 61 72 79 20 43 6F 64 65 64 20 44 65 63 ♪•FBSTP û Store Binary Coded Dec 00012440 69 6D 61 6C 20 61 6E 64 20 50 6F 70 0D 07 4E 50 0D 07 0D 07 46 43 48 53 20 96 20 43 68 61 6E 67 imal and Pop♪•NP♪•♪•FCHS û Chang 00012460 65 20 53 69 67 6E 0D 07 46 58 0D 07 0D 07 46 43 4C 45 58 20 96 20 43 6C 65 61 72 20 45 78 63 65 e Sign♪•FX♪•♪•FCLEX û Clear Exce 00012480 70 74 69 6F 6E 73 0D 07 4E 50 0D 07 0D 07 46 43 4F 4D 20 96 20 43 6F 6D 70 61 72 65 20 52 65 61 ptions♪•NP♪•♪•FCOM û Compare Rea 000124A0 6C 0D 07 46 58 0D 07 0D 07 46 43 4F 4D 50 20 96 20 43 6F 6D 70 61 72 65 20 52 65 61 6C 20 61 6E l♪•FX♪•♪•FCOMP û Compare Real an 000124C0 64 20 50 6F 70 0D 07 46 58 0D 07 0D 07 46 43 4F 4D 50 50 20 96 20 43 6F 6D 70 61 72 65 20 52 65 d Pop♪•FX♪•♪•FCOMPP û Compare Re 000124E0 61 6C 20 61 6E 64 20 50 6F 70 20 54 77 69 63 65 0D 07 0D 07 0D 07 46 43 4F 53 20 96 20 43 6F 73 al and Pop Twice♪•♪•♪•FCOS û Cos 00012500 69 6E 65 20 6F 66 20 53 54 28 30 29 0D 07 4E 50 0D 07 0D 07 46 44 45 43 53 54 50 20 96 20 44 65 ine of ST(0)♪•NP♪•♪•FDECSTP û De 00012520 63 72 65 6D 65 6E 74 20 53 74 61 63 6B 2D 54 6F 70 20 50 6F 69 6E 74 65 72 0D 07 4E 50 0D 07 0D crement Stack-Top Pointer♪•NP♪•♪ 00012540 07 46 44 49 56 20 96 20 44 69 76 69 64 65 0D 07 46 58 0D 07 0D 07 46 44 49 56 50 20 96 20 44 69 •FDIV û Divide♪•FX♪•♪•FDIVP û Di 00012560 76 69 64 65 20 61 6E 64 20 50 6F 70 0D 07 46 58 0D 07 0D 07 46 44 49 56 52 20 96 20 52 65 76 65 vide and Pop♪•FX♪•♪•FDIVR û Reve 00012580 72 73 65 20 44 69 76 69 64 65 0D 07 46 58 0D 07 0D 07 46 44 49 56 52 50 20 96 20 52 65 76 65 72 rse Divide♪•FX♪•♪•FDIVRP û Rever 000125A0 73 65 20 44 69 76 69 64 65 20 61 6E 64 20 50 6F 70 0D 07 46 58 0D 07 0D 07 46 46 52 45 45 20 96 se Divide and Pop♪•FX♪•♪•FFREE û 000125C0 20 46 72 65 65 20 53 54 28 69 29 20 52 65 67 69 73 74 65 72 0D 07 4E 50 0D 07 0D 07 46 49 41 44 Free ST(i) Register♪•NP♪•♪•FIAD 000125E0 44 20 96 20 41 64 64 20 49 6E 74 65 67 65 72 0D 07 4E 50 0D 07 0D 07 46 49 43 4F 4D 20 96 20 43 D û Add Integer♪•NP♪•♪•FICOM û C 00012600 6F 6D 70 61 72 65 20 49 6E 74 65 67 65 72 0D 07 4E 50 0D 07 0D 07 46 49 43 4F 4D 50 20 96 20 43 ompare Integer♪•NP♪•♪•FICOMP û C 00012620 6F 6D 70 61 72 65 20 49 6E 74 65 67 65 72 20 61 6E 64 20 50 6F 70 0D 07 4E 50 0D 07 0D 07 46 49 ompare Integer and Pop♪•NP♪•♪•FI 00012640 44 49 56 0D 07 4E 50 0D 07 0D 07 46 49 44 49 56 52 0D 07 4E 50 0D 07 0D 07 46 49 4C 44 20 96 20 DIV♪•NP♪•♪•FIDIVR♪•NP♪•♪•FILD û 00012660 4C 6F 61 64 20 49 6E 74 65 67 65 72 0D 07 4E 50 0D 07 0D 07 46 49 4D 55 4C 0D 07 4E 50 0D 07 0D Load Integer♪•NP♪•♪•FIMUL♪•NP♪•♪ 00012680 07 46 49 4E 43 53 54 50 20 96 20 49 6E 63 72 65 6D 65 6E 74 20 53 74 61 63 6B 20 50 6F 69 6E 74 •FINCSTP û Increment Stack Point 000126A0 65 72 0D 07 4E 50 0D 07 0D 07 46 49 4E 49 54 20 96 20 49 6E 69 74 69 61 6C 69 7A 65 20 46 6C 6F er♪•NP♪•♪•FINIT û Initialize Flo 000126C0 61 74 69 6E 67 2D 50 6F 69 6E 74 20 55 6E 69 74 0D 07 4E 50 0D 07 0D 07 46 49 53 54 20 96 20 53 ating-Point Unit♪•NP♪•♪•FIST û S 000126E0 74 6F 72 65 20 49 6E 74 65 67 65 72 0D 07 4E 50 0D 07 0D 07 46 49 53 54 50 20 96 20 53 74 6F 72 tore Integer♪•NP♪•♪•FISTP û Stor 00012700 65 20 49 6E 74 65 67 65 72 20 61 6E 64 20 50 6F 70 0D 07 4E 50 0D 07 0D 07 46 49 53 55 42 0D 07 e Integer and Pop♪•NP♪•♪•FISUB♪• 00012720 4E 50 0D 07 0D 07 46 49 53 55 42 52 0D 07 4E 50 0D 07 0D 07 46 4C 44 20 96 20 4C 6F 61 64 20 52 NP♪•♪•FISUBR♪•NP♪•♪•FLD û Load R 00012740 65 61 6C 0D 07 0D 07 0D 07 A0 A0 A0 33 32 2D 62 69 74 20 6D 65 6D 6F 72 79 09 31 31 30 31 31 20 eal♪•♪•♪•ááá32-bit memory○11011 00012760 30 30 31 20 3A 20 6D 6F 64 20 30 30 30 20 72 2F 6D 0D 07 46 58 0D 07 0D 07 A0 A0 A0 36 34 2D 62 001 : mod 000 r/m♪•FX♪•♪•ááá64-b 00012780 69 74 20 6D 65 6D 6F 72 79 09 31 31 30 31 31 20 31 30 31 20 3A 20 6D 6F 64 20 30 30 30 20 72 2F it memory○11011 101 : mod 000 r/ 000127A0 6D 0D 07 46 58 0D 07 0D 07 A0 A0 A0 38 30 2D 62 69 74 20 6D 65 6D 6F 72 79 09 31 31 30 31 31 20 m♪•FX♪•♪•ááá80-bit memory○11011 000127C0 30 31 31 20 3A 20 6D 6F 64 20 31 30 31 20 72 2F 6D 0D 07 4E 50 0D 07 0D 07 A0 A0 A0 53 54 28 69 011 : mod 101 r/m♪•NP♪•♪•áááST(i 000127E0 29 09 31 31 30 31 31 20 30 30 31 20 3A 20 31 31 20 30 30 30 20 53 54 28 69 29 0D 07 46 58 0D 07 )○11011 001 : 11 000 ST(i)♪•FX♪• 00012800 0D 07 46 4C 44 31 20 96 20 4C 6F 61 64 20 2B 31 2E 30 20 69 6E 74 6F 20 53 54 28 30 29 0D 07 4E ♪•FLD1 û Load +1.0 into ST(0)♪•N 00012820 50 0D 07 0D 07 46 4C 44 43 57 20 96 20 4C 6F 61 64 20 43 6F 6E 74 72 6F 6C 20 57 6F 72 64 0D 07 P♪•♪•FLDCW û Load Control Word♪• 00012840 4E 50 0D 07 0D 07 46 4C 44 45 4E 56 20 96 20 4C 6F 61 64 20 46 50 55 20 45 6E 76 69 72 6F 6E 6D NP♪•♪•FLDENV û Load FPU Environm 00012860 65 6E 74 0D 07 4E 50 0D 07 0D 07 46 4C 44 4C 32 45 20 96 20 4C 6F 61 64 20 6C 6F 67 32 28 13 53 ent♪•NP♪•♪•FLDL2E û Load log2(‼S 00012880 59 4D 42 4F 4C 20 31 30 31 20 5C 66 20 22 53 79 6D 62 6F 6C 22 15 29 20 69 6E 74 6F 20 53 54 28 YMBOL 101 \f "Symbol"§) into ST( 000128A0 30 29 0D 07 4E 50 0D 07 0D 07 46 4C 44 4C 32 54 20 96 20 4C 6F 61 64 20 6C 6F 67 32 28 31 30 29 0)♪•NP♪•♪•FLDL2T û Load log2(10) 000128C0 20 69 6E 74 6F 20 53 54 28 30 29 0D 07 4E 50 0D 07 0D 07 0C 46 6C 6F 61 74 69 6E 67 2D 50 6F 69 into ST(0)♪•NP♪•♪•♀Floating-Poi 000128E0 6E 74 20 49 6E 73 74 72 75 63 74 69 6F 6E 20 50 61 69 72 69 6E 67 20 28 43 6F 6E 74 69 6E 75 65 nt Instruction Pairing (Continue 00012900 64 29 0D 0A 49 4E 53 54 52 55 43 54 49 4F 4E 09 46 4F 52 4D 41 54 0D 07 50 61 69 72 69 6E 67 0D d)♪◙INSTRUCTION○FORMAT♪•Pairing♪ 00012920 07 0D 07 46 4C 44 4C 47 32 20 96 20 4C 6F 61 64 20 6C 6F 67 31 30 28 32 29 20 69 6E 74 6F 20 53 •♪•FLDLG2 û Load log10(2) into S 00012940 54 28 30 29 0D 07 4E 50 0D 07 0D 07 46 4C 44 4C 4E 32 20 96 20 4C 6F 61 64 20 6C 6F 67 13 53 59 T(0)♪•NP♪•♪•FLDLN2 û Load log‼SY 00012960 4D 42 4F 4C 20 31 30 31 20 5C 66 20 22 53 79 6D 62 6F 6C 22 15 28 32 29 20 69 6E 74 6F 20 53 54 MBOL 101 \f "Symbol"§(2) into ST 00012980 28 30 29 0D 07 4E 50 0D 07 0D 07 46 4C 44 50 49 20 96 20 4C 6F 61 64 20 13 53 59 4D 42 4F 4C 20 (0)♪•NP♪•♪•FLDPI û Load ‼SYMBOL 000129A0 31 31 32 20 5C 66 20 22 53 79 6D 62 6F 6C 22 15 20 69 6E 74 6F 20 53 54 28 30 29 0D 07 4E 50 0D 112 \f "Symbol"§ into ST(0)♪•NP♪ 000129C0 07 0D 07 46 4C 44 5A 20 96 20 4C 6F 61 64 20 2B 30 2E 30 20 69 6E 74 6F 20 53 54 28 30 29 0D 07 •♪•FLDZ û Load +0.0 into ST(0)♪• 000129E0 4E 50 0D 07 0D 07 46 4D 55 4C 20 96 20 4D 75 6C 74 69 70 6C 79 0D 07 46 58 0D 07 0D 07 46 4D 55 NP♪•♪•FMUL û Multiply♪•FX♪•♪•FMU 00012A00 4C 50 20 96 20 4D 75 6C 74 69 70 6C 79 0D 07 46 58 0D 07 0D 07 46 4E 4F 50 20 96 20 4E 6F 20 4F LP û Multiply♪•FX♪•♪•FNOP û No O 00012A20 70 65 72 61 74 69 6F 6E 0D 07 4E 50 0D 07 0D 07 46 50 41 54 41 4E 20 96 20 50 61 72 74 69 61 6C peration♪•NP♪•♪•FPATAN û Partial 00012A40 20 41 72 63 74 61 6E 67 65 6E 74 0D 07 4E 50 0D 07 0D 07 46 50 52 45 4D 20 96 20 50 61 72 74 69 Arctangent♪•NP♪•♪•FPREM û Parti 00012A60 61 6C 20 52 65 6D 61 69 6E 64 65 72 0D 07 4E 50 0D 07 0D 07 46 50 52 45 4D 31 20 96 20 50 61 72 al Remainder♪•NP♪•♪•FPREM1 û Par 00012A80 74 69 61 6C 20 52 65 6D 61 69 6E 64 65 72 20 28 49 45 45 45 29 0D 07 4E 50 0D 07 0D 07 46 50 54 tial Remainder (IEEE)♪•NP♪•♪•FPT 00012AA0 41 4E 20 96 20 50 61 72 74 69 61 6C 20 54 61 6E 67 65 6E 74 0D 07 4E 50 0D 07 0D 07 46 52 4E 44 AN û Partial Tangent♪•NP♪•♪•FRND 00012AC0 49 4E 54 20 96 20 52 6F 75 6E 64 20 74 6F 20 49 6E 74 65 67 65 72 0D 07 0D 07 0D 07 46 52 53 54 INT û Round to Integer♪•♪•♪•FRST 00012AE0 4F 52 20 96 20 52 65 73 74 6F 72 65 20 46 50 55 20 53 74 61 74 65 0D 07 4E 50 0D 07 0D 07 46 53 OR û Restore FPU State♪•NP♪•♪•FS 00012B00 41 56 45 20 96 20 53 74 6F 72 65 20 46 50 55 20 53 74 61 74 65 0D 07 4E 50 0D 07 0D 07 46 53 43 AVE û Store FPU State♪•NP♪•♪•FSC 00012B20 41 4C 45 20 96 20 53 63 61 6C 65 0D 07 4E 50 0D 07 0D 07 46 53 49 4E 20 96 20 53 69 6E 65 0D 07 ALE û Scale♪•NP♪•♪•FSIN û Sine♪• 00012B40 4E 50 0D 07 0D 07 46 53 49 4E 43 4F 53 20 96 20 53 69 6E 65 20 61 6E 64 20 43 6F 73 69 6E 65 0D NP♪•♪•FSINCOS û Sine and Cosine♪ 00012B60 07 4E 50 0D 07 0D 07 46 53 51 52 54 20 96 20 53 71 75 61 72 65 20 52 6F 6F 74 0D 07 4E 50 0D 07 •NP♪•♪•FSQRT û Square Root♪•NP♪• 00012B80 0D 07 46 53 54 20 96 20 53 74 6F 72 65 20 52 65 61 6C 0D 07 4E 50 0D 07 0D 07 46 53 54 43 57 20 ♪•FST û Store Real♪•NP♪•♪•FSTCW 00012BA0 96 20 53 74 6F 72 65 20 43 6F 6E 74 72 6F 6C 20 57 6F 72 64 0D 07 4E 50 0D 07 0D 07 46 53 54 45 û Store Control Word♪•NP♪•♪•FSTE 00012BC0 4E 56 20 96 20 53 74 6F 72 65 20 46 50 55 20 45 6E 76 69 72 6F 6E 6D 65 6E 74 0D 07 4E 50 0D 07 NV û Store FPU Environment♪•NP♪• 00012BE0 0D 07 46 53 54 50 20 96 20 53 74 6F 72 65 20 52 65 61 6C 20 61 6E 64 20 50 6F 70 0D 07 4E 50 0D ♪•FSTP û Store Real and Pop♪•NP♪ 00012C00 07 0D 07 46 53 54 53 57 20 96 20 53 74 6F 72 65 20 53 74 61 74 75 73 20 57 6F 72 64 20 69 6E 74 •♪•FSTSW û Store Status Word int 00012C20 6F 20 41 58 0D 07 4E 50 0D 07 0D 07 46 53 54 53 57 20 96 20 53 74 6F 72 65 20 53 74 61 74 75 73 o AX♪•NP♪•♪•FSTSW û Store Status 00012C40 20 57 6F 72 64 20 69 6E 74 6F 20 4D 65 6D 6F 72 79 0D 07 4E 50 0D 07 0D 07 46 53 55 42 20 96 20 Word into Memory♪•NP♪•♪•FSUB û 00012C60 53 75 62 74 72 61 63 74 0D 07 46 58 0D 07 0D 07 46 53 55 42 50 20 96 20 53 75 62 74 72 61 63 74 Subtract♪•FX♪•♪•FSUBP û Subtract 00012C80 20 61 6E 64 20 50 6F 70 0D 07 46 58 0D 07 0D 07 46 53 55 42 52 20 96 20 52 65 76 65 72 73 65 20 and Pop♪•FX♪•♪•FSUBR û Reverse 00012CA0 53 75 62 74 72 61 63 74 0D 07 46 58 0D 07 0D 07 46 53 55 42 52 50 20 96 20 52 65 76 65 72 73 65 Subtract♪•FX♪•♪•FSUBRP û Reverse 00012CC0 20 53 75 62 74 72 61 63 74 20 61 6E 64 20 50 6F 70 0D 07 46 58 0D 07 0D 07 46 54 53 54 20 96 20 Subtract and Pop♪•FX♪•♪•FTST û 00012CE0 54 65 73 74 0D 07 46 58 0D 07 0D 07 46 55 43 4F 4D 20 96 20 55 6E 6F 72 64 65 72 65 64 20 43 6F Test♪•FX♪•♪•FUCOM û Unordered Co 00012D00 6D 70 61 72 65 20 52 65 61 6C 29 0D 07 46 58 0D 07 0D 07 46 55 43 4F 4D 50 20 96 20 55 6E 6F 72 mpare Real)♪•FX♪•♪•FUCOMP û Unor 00012D20 64 65 72 65 64 20 43 6F 6D 70 61 72 65 20 61 6E 64 20 50 6F 70 0D 07 46 58 0D 07 0D 07 46 55 43 dered Compare and Pop♪•FX♪•♪•FUC 00012D40 4F 4D 50 50 20 96 20 55 6E 6F 72 64 65 72 65 64 20 43 6F 6D 70 61 72 65 20 20 61 6E 64 20 50 6F OMPP û Unordered Compare and Po 00012D60 70 20 54 77 69 63 65 0D 07 46 58 0D 07 0D 07 46 58 41 4D 20 96 20 45 78 61 6D 69 6E 65 0D 07 4E p Twice♪•FX♪•♪•FXAM û Examine♪•N 00012D80 50 0D 07 0D 07 46 58 43 48 20 96 20 45 78 63 68 61 6E 67 65 20 53 54 28 30 29 20 61 6E 64 20 53 P♪•♪•FXCH û Exchange ST(0) and S 00012DA0 54 28 69 29 0D 07 0D 07 0D 07 46 58 54 52 41 43 54 20 96 20 45 78 74 72 61 63 74 20 45 78 70 6F T(i)♪•♪•♪•FXTRACT û Extract Expo 00012DC0 6E 65 6E 74 20 20 61 6E 64 20 53 69 67 6E 69 66 69 63 61 6E 64 0D 07 4E 50 0D 07 0D 07 46 59 4C nent and Significand♪•NP♪•♪•FYL 00012DE0 32 58 20 96 20 53 54 28 31 29 20 13 53 59 4D 42 4F 4C 20 31 38 30 20 5C 66 20 22 53 79 6D 62 6F 2X û ST(1) ‼SYMBOL 180 \f "Symbo 00012E00 6C 22 15 20 6C 6F 67 32 28 53 54 28 30 29 29 0D 07 4E 50 0D 07 0D 07 46 59 4C 32 58 50 31 20 96 l"§ log2(ST(0))♪•NP♪•♪•FYL2XP1 û 00012E20 20 53 54 28 31 29 20 13 53 59 4D 42 4F 4C 20 31 38 30 20 5C 66 20 22 53 79 6D 62 6F 6C 22 15 20 ST(1) ‼SYMBOL 180 \f "Symbol"§ 00012E40 6C 6F 67 32 28 53 54 28 30 29 20 2B 20 31 2E 30 29 0D 07 4E 50 0D 07 0D 07 46 57 41 49 54 20 96 log2(ST(0) + 1.0)♪•NP♪•♪•FWAIT û 00012E60 20 57 61 69 74 20 75 6E 74 69 6C 20 46 50 55 20 52 65 61 64 79 0D 07 0D 07 0D 07 0D 0A 0D 0A 02 Wait until FPU Ready♪•♪•♪•♪◙♪◙☻ 00012E80 20 20 54 68 69 73 20 73 65 74 20 69 6E 63 6C 75 64 65 73 20 61 6C 73 6F 20 74 68 65 20 66 61 64 This set includes also the fad 00012EA0 64 70 2C 20 66 73 75 62 72 70 2C 20 2E 2E 2E 20 69 6E 73 74 72 75 63 74 69 6F 6E 73 0D 0A 0D 0A dp, fsubrp, ... instructions♪◙♪◙ 00012EC0 0D 0A 09 0D 0A 0D 0A 4F 70 74 69 6D 69 7A 61 74 69 6F 6E 73 20 66 6F 72 20 49 6E 74 65 6C 27 73 ♪◙○♪◙♪◙Optimizations for Intel's 00012EE0 20 33 32 2D 42 69 74 20 50 72 6F 63 65 73 73 6F 72 73 20 20 20 20 20 20 20 20 20 20 20 20 20 20 32-Bit Processors 00012F00 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 00012F20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 56 65 72 73 69 6F 6E 20 32 2E 30 0D 0A 0D 0A Version 2.0♪◙♪◙ 00012F40 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 00012F60 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 00012F80 20 20 20 20 20 20 20 20 20 20 20 20 50 61 67 65 20 20 13 50 41 47 45 14 32 33 15 0D 0A 0D 0A 49 Page ‼PAGE¶23§♪◙♪◙I 00012FA0 6E 74 65 6C 20 43 6F 6E 66 69 64 65 6E 74 69 61 6C 09 09 50 61 67 65 20 13 50 41 47 45 14 33 15 ntel Confidential○○Page ‼PAGE¶3§ 00012FC0 0D 0A 0D 0A 09 49 6E 73 74 72 75 63 74 69 6F 6E 20 50 61 69 72 69 6E 67 20 53 75 6D 6D 61 72 79 ♪◙♪◙○Instruction Pairing Summary 00012FE0 09 0D 0A 01 0D 0A 0D 0A 0D 0A 0D 0A 09 41 2D 13 50 41 47 45 14 39 15 0D 0A 0D 0A 09 41 2D 13 50 ○♪◙☺♪◙♪◙♪◙♪◙○A-‼PAGE¶9§♪◙♪◙○A-‼P 00013000 41 47 45 14 31 15 0D 0A 0D 0A 0D 0A 0D 0A 08 80 08 8D A0 05 8E A0 05 0D 88 01 00 7D 01 80 2A 8D AGE¶1§♪◙♪◙♪◙♪◙◘Ç◘ìá♣Äá♣♪ê☺.}☺Ç*ì 00013020 A0 05 8E A0 05 17 75 04 76 01 88 01 00 7D 01 80 2E 8D A0 05 8E A0 05 73 00 F0 74 00 F0 3A 20 31 á♣Äá♣↨u♦v☺ê☺.}☺Ç.ìá♣Äá♣s.≡t.≡: 1 00013040 BA 06 00 00 3A 00 08 00 51 34 F3 05 7E 2E 00 00 00 00 00 00 00 00 00 00 00 00 00 00 AA 1D 60 03 ║♠..:.◘.Q4≤♣~...............¬↔`♥ 00013060 E1 03 E1 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 00 01 ß♥ß♥......................☺.○..☺ 00013080 35 03 00 00 04 00 60 01 00 00 00 00 04 00 00 00 03 01 08 00 05 00 00 00 0C 02 B4 00 2E 06 05 00 5♥..♦.`☺....♦...♥☺◘.♣...♀☻┤..♠♣. 000130A0 00 00 0B 02 FF FF FF FF 0D 00 00 00 26 06 0F 00 0F 00 43 72 65 61 74 6F 72 3A 20 4D 47 58 57 4D ..♂☻ ♪...&♠☼.☼.Creator: MGXWM 000130C0 46 00 1A 00 00 00 26 06 0F 00 2A 00 43 6F 6D 70 61 74 69 62 6C 65 20 77 69 74 68 20 50 53 43 52 F.→...&♠☼.*.Compatible with PSCR 000130E0 49 50 54 2C 50 6F 73 74 53 63 72 69 70 74 20 50 72 69 6E 74 65 72 04 00 00 00 02 01 02 00 05 00 IPT,PostScript Printer♦...☻☺☻.♣. 00013100 00 00 01 02 FF FF FF 00 04 00 00 00 04 01 0D 00 04 00 00 00 05 01 01 00 04 00 00 00 06 01 01 00 ..☺☻ .♦...♦☺♪.♦...♣☺☺.♦...♠☺☺. 00013120 08 00 00 00 FA 02 05 00 00 00 00 00 FF FF FF 00 04 00 00 00 2D 01 00 00 07 00 00 00 FC 02 00 00 ◘...·☻♣..... .♦...-☺..•...ⁿ☻.. 00013140 00 00 00 00 00 00 04 00 00 00 2D 01 01 00 04 00 00 00 04 01 0D 00 0E 00 00 00 24 03 05 00 13 00 ......♦...-☺☺.♦...♦☺♪.♫...$♥♣.‼. 00013160 0E 00 13 00 00 00 03 00 00 00 03 00 0E 00 13 00 0E 00 0E 00 00 00 24 03 05 00 13 00 55 00 13 00 ♫.‼...♥...♥.♫.‼.♫.♫...$♥♣.‼.U.‼. 00013180 16 00 03 00 16 00 03 00 55 00 13 00 55 00 78 00 00 00 24 03 3A 00 2F 00 2A 00 2F 00 29 00 30 00 ▬.♥.▬.♥.U.‼.U.x...$♥:./.*./.).0. 000131A0 29 00 31 00 28 00 31 00 26 00 33 00 26 00 33 00 25 00 34 00 25 00 35 00 24 00 3E 00 24 00 3E 00 ).1.(.1.&.3.&.3.%.4.%.5.$.>.$.>. 000131C0 25 00 40 00 25 00 40 00 26 00 41 00 27 00 42 00 27 00 42 00 29 00 43 00 29 00 43 00 2C 00 44 00 %.@.%.@.&.A.'.B.'.B.).C.).C.,.D. 000131E0 2C 00 44 00 55 00 54 00 55 00 54 00 25 00 53 00 24 00 53 00 23 00 52 00 22 00 52 00 20 00 51 00 ,.D.U.T.U.T.%.S.$.S.#.R.".R. .Q. 00013200 20 00 51 00 1D 00 50 00 1D 00 4D 00 1A 00 4C 00 1A 00 4C 00 19 00 4B 00 18 00 4A 00 18 00 49 00 .Q.↔.P.↔.M.→.L.→.L.↓.K.↑.J.↑.I. 00013220 17 00 48 00 17 00 47 00 16 00 44 00 16 00 43 00 15 00 3B 00 15 00 3A 00 16 00 37 00 16 00 35 00 ↨.H.↨.G.▬.D.▬.C.§.;.§.:.▬.7.▬.5. 00013240 18 00 33 00 18 00 33 00 1A 00 31 00 1A 00 31 00 1B 00 2F 00 1D 00 2F 00 1F 00 2E 00 1F 00 2E 00 ↑.3.↑.3.→.1.→.1.←./.↔./.▼...▼... 00013260 20 00 2E 00 16 00 1E 00 16 00 1E 00 55 00 2E 00 55 00 2E 00 2C 00 2F 00 2C 00 2F 00 2A 00 60 01 ...▬.▲.▬.▲.U...U...,./.,./.*.`☺ 00013280 00 00 24 03 AE 00 8A 00 48 00 A5 00 48 00 A5 00 45 00 A4 00 45 00 A4 00 42 00 A3 00 41 00 A3 00 ..$♥«.è.H.Ñ.H.Ñ.E.ñ.E.ñ.B.ú.A.ú. 000132A0 40 00 A2 00 40 00 A1 00 3F 00 A1 00 3E 00 9F 00 3E 00 9F 00 3D 00 9E 00 3D 00 9D 00 3C 00 9B 00 @.ó.@.í.?.í.>.ƒ.>.ƒ.=.₧.=.¥.<.¢. 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