HP28S PROCESSOR INSTRUCTION SET Version 1
Copyright (C) 1989, Alonzo Gariepy
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== INSTRUCTIONS BY NUMBER ==
== ==
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Here is a list of HP28 opcodes in numerical order. While the
separation lines help in navigation, their primary purpose is
to delimit the scope of each set of substitution tables.
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00 RETSETXM
01 RET
02 RETSETC
03 RETCLRC
04 SETHEX
05 SETDEC
06 PUSH.A C ***
07 POP.A C ***
08 CLR.X ST ***
09 MOVE.X ST,C ***
0A MOVE.X C,ST ***
0B SWAP.X C,ST ***
0C INC.1 P ***
0D DEC.1 P ***
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0Exy AND.f s,d
0Exz OR.f s,d
x | f y z | s d
------- -----------
0 | P 0 8 | B A
1 | WP 1 9 | C B
2 | XS 2 A | A C
3 | X 3 B | C D
4 | S 4 C | A B
5 | M 5 D | B C
6 | B 6 E | C A
7 | W 7 F | D C
F | A
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0F RETI
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10j MOVE.W A,Rn ***
10k MOVE.W C,Rn ***
11j MOVE.W Rn,A ***
11k MOVE.W Rn,C ***
12j SWAP.W A,Rn ***
12k SWAP.W C,Rn ***
j k | Rn
----------
0 8 | R0
1 9 | R1
2 A | R2
3 B | R3
4 C | R4
________________________________________________________________
13w MOVE.A s,Dn ***
13x SWAP.A s,Dn ***
13y MOVE.4 s,Dn
13z SWAP.4 s,Dn
w x y z | s Dn
----------------
0 2 8 A | A D0
1 3 9 B | A D1
4 6 C E | C D0
5 7 D F | C D1
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14x MOVE.A s,d
14y MOVE.B s,d
15xt MOVE.f s,d
15yi MOVE.n s,d ; n = i + 1
x y | s d t | f
--------------- -------
0 8 | A @D0 0 | P
1 9 | A @D1 1 | WP
2 A | @D0 A 2 | XS
3 B | @D1 A 3 | X
4 C | C @D0 4 | S
5 D | C @D1 5 | M
6 E | @D0 C 6 | B
7 F | @D1 C 7 | W
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16x ADD.A x+1,D0 ***
17x ADD.A x+1,D1 ***
18x SUB.A x+1,D0 ***
19xx MOVE.2 xx,D0
1Axxxx MOVE.4 xxxx,D0
1Bxxxxx MOVE.5 xxxxx,D0
1Cx SUB.A x+1,D1 ***
1Dxx MOVE.2 xx,D1
1Exxxx MOVE.4 xxxx,D1
1Fxxxxx MOVE.5 xxxxx,D1
2x MOVE.1 x,P ***
3ix...x MOVE.Pn x...x,C ; n = i + 1
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4xx BRCS PC+1+xx
420 NOP3
5xx BRCC PC+1+xx
6xxx JUMP.3 PC+1+xxx ***
6300 NOP4
64000 NOP5
7xxx CALL.3 PC+4+xxx ***
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800 OUT.S C
801 OUT.X C
802 IN.4 A ***
803 IN.4 C ***
804 UNCNFG
805 CONFIG
806 MOVE.A ID,C
807 SHUTDN
8080 INTON
80810 RSI
8082ix...x MOVE.Pn x...x,A ; n = i + 1
8083 BUSCB
8084x CLRB x,A
8085x SETB x,A
8086xyy BRBC x,A,PC+5+yy
8087xyy BRBS x,A,PC+5+yy
8088x CLRB x,C
8089x SETB x,C
808Axyy BRBC x,C,PC+5+yy
808Bxyy BRBS x,C,PC+5+yy
808C JUMP.A @A ***
808C MOVE.A @A,PC ***
808D BUSCD
808E JUMP.A @C ***
808E MOVE.A @C,PC ***
808F INTOFF
809 ADD.A P+1,C
80A RESET
80B BUSCC
80Cx MOVE.1 P,C,x ***
80Dx MOVE.1 C,x,P ***
80E SREQ
80Fx SWAP.1 P,C,x ***
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81w RLN.W d
81x RRN.W d
818twi ADD.f i+1,d
818tyi SUB.f i+1,d
819tw SRB.f d
81At0j MOVE.f A,Rn
81At0k MOVE.f C,Rn
81At1j MOVE.f Rn,A
81At1k MOVE.f Rn,C
81At2j SWAP.f A,Rn
81At2k SWAP.f C,Rn
81z SRB.W d
t | f w x y z | d j k | Rn
------- ------------- ----------
0 | P 0 4 8 C | A 0 8 | R0
1 | WP 1 5 9 D | B 1 9 | R1
2 | XS 2 6 A E | C 2 A | R2
3 | X 3 7 B F | D 3 B | R3
4 | S 4 C | R4
5 | M
6 | B
7 | W
F | A
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81B2 JUMP.A A ***
81B2 MOVE.A A,PC ***
81B3 JUMP.A C ***
81B3 MOVE.A C,PC ***
81B4 MOVE.A PC,A ***
81B5 MOVE.A PC,C ***
81B6 SWAP.A A,PC ***
81B7 SWAP.A C,PC ***
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82x CLRB d*
83xyy BRBC d,PC+3+yy
x | d
--------
1 | XM
2 | SB
4 | SR
8 | MP
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84x CLRB x,ST
85x SETB x,ST
86xyy BRBC x,ST,PC+3+yy
87xyy BRBS x,ST,PC+3+yy
88xyy BRNE.1 P,x,PC+3+yy ***
89xyy BREQ.1 P,x,PC+3+yy ***
________________________________________________________________
ttuyy BREQ.f s,d,PC+3+yy
ttvyy BRNE.f s,d,PC+3+yy
ttwyy BRZ.f s,PC+3+yy
ttxyy BRNZ.f s,PC+3+yy
zzuyy BRGT.f s,d,PC+3+yy
zzvyy BRLT.f s,d,PC+3+yy
zzwyy BRGE.f s,d,PC+3+yy
zzxyy BRLE.f s,d,PC+3+yy
tt zz | f u v w x | s d
----------- ---------------
8A 8B | A 0 4 8 C | A B
90 98 | P 1 5 9 D | B C
91 99 | WP 2 6 A E | C A
92 9A | XS 3 7 B F | D C
93 9B | X
94 9C | S
95 9D | M
96 9E | B
97 9F | W
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8Cxxxx JUMP.4 PC+2+xxxx
8Dxxxxx JUMP.A xxxxx
8Exxxx CALL.4 PC+6+xxxx
8Fxxxxx CALL.A xxxxx
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kkx ADD.f s,d
kkw DEC.f d
ppt CLR.f d
ppz MOVE.f s,d
ppw SWAP.f s,d
qqy SUB.f s,d
qqu INC.f d
qqw SUBN.f s,d
rrt SLN.f d
rru SRN.f d
rrv NEG.f d
rrw NOT.f d
kk pp qq rr | f t u v w x y z | s d
----------------- ---------------------
A0 A8 B0 B8 | P 0 4 8 C 0 0 4 | B A
A1 A9 B1 B9 | WP 1 5 9 D 1 1 5 | C B
A2 AA B2 BA | XS 2 6 A E 2 2 6 | A C
A3 AB B3 BB | X 3 7 B F 3 3 7 | C D
A4 AC B4 BC | S 4 | A A
A5 AD B5 BD | M 5 | B B
A6 AE B6 BE | B 6 | C C
A7 AF B7 BF | W 7 | D D
C D E F | A 8 8 8 | A B
9 9 9 | B C
A A A | C A
B B B | D C
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== INSTRUCTIONS WITH DEFAULT FIELD SUFFIXES ==
== ==
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Here is a summary of all instructions in which you may omit the
field suffix after the name. These instructions are marked with
*** in the numeric and alphabetic listings. This summary uses
the following abbreviations: ac = A or C; Dn = D0 or D1; Rn =
R0, R1, R2, R3, or R4. These are the only instructions in which
you can omit the field suffix:
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.A Instructions that reference D0, D1, PC, or RSTK use
the Address Field by default when you omit the .A
suffix:
PUSH C
POP C
MOVE ac,Dn
SWAP ac,Dn
ADD const,Dn
SUB const,Dn
JUMP @ac
MOVE @ac,PC
JUMP ac
MOVE ac,PC
MOVE PC,ac
SWAP ac,PC
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.1 Instructions that reference P use a one nibble field by
default when you omit the .1 suffix:
BREQ P,x,PC+3+offset
BRNE P,x,PC+3+offset
DEC P
INC P
MOVE x,P
MOVE P,C,i
MOVE C,i,P
RETEQ P,x
RETNE P,x
SWAP P,C,i
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.W Instructions that reference the temporary registers use
the entire word by default when you omit the .W suffix:
MOVE ac,Rn
MOVE Rn,ac
SWAP ac,Rn
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.3 You can omit the .3 suffix from relative JUMP and CALL
instructions that use three nibble offsets:
JUMP PC+1+offset
CALL PC+4+offset
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.X Instructions that reference ST use a three nibble field
by default so you can omit the .X suffix:
CLR ST
MOVE C,ST
MOVE ST,C
SWAP C,ST
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.4 The IN instruction only uses a four nibble field so you
can omit the .4 suffix:
IN ac
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Here is a list of all the instructions that never take a suffix:
BRBC BUSCD NOP4 RETCC SETB
BRBS CLRB NOP5 RETCLRC SETDEC
BRCC CONFIG RESET RETCS SETHEX
BRCS INTOFF RET RETSETC SHUTDN
BUSCB INTON RETBC RETSETXM SREQ
BUSCC NOP3 RETBS RSI UNCNFG
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ALL OTHER INSTRUCTIONS REQUIRE A FIELD SUFFIX.
The following instructions are similar to ones above
but do require a field suffix:
ADD.A P+1,C
OUT.S C
OUT.X C
MOVE.2 const,Dn
MOVE.4 const,Dn
MOVE.5 const,Dn
MOVE.4 ac,Dn
JUMP.4 PC+2+offset
CALL.4 PC+2+offset
CALL.A const
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== ==
== INSTRUCTIONS BY TYPE ==
== ==
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ADD
================================================================
ADD Register to Register
kkx ADD.f s,d
kk | f x | s d
-------- ---------
A0 | P 0 | B A
A1 | WP 1 | C B
A2 | XS 2 | A C
A3 | X 3 | C D
A4 | S 4 | A A
A5 | M 5 | B B
A6 | B 6 | C C
A7 | W 7 | D D
C | A 8 | A B
9 | B C
A | C A
B | D C
Examples:
C8 ADD.A A,B ; B = B + A (20 bits)
A70 ADD.W B,A ; A = A + B (64 bits)
A36 ADD.X C,C ; C = C + C (12 bits)
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ADD Constant to Register
"The 818... opcodes don't always work as advertised.
To be specific, when the field of such an instruction
is XS, S, P, or WP, and a carry (or borrow) is generated
out of the most significant nibble, it wraps around and
affects the least significant nibble." -- D.K.
818twi ADD.f i+1,d
t | f x | d
------- -------
0 | P 0 | A
1 | WP 1 | B
2 | XS 2 | C
3 | X 3 | D
4 | S
5 | M
6 | B
7 | W
F | A
Examples:
818718 ADD.W 9,B ; B = B + 9 (64 bits)
81860F ADD.B 16,A ; A = A + 16 (8 bits)
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ADD Constant to Address Register
These instructions let you add a constant from 1 to 16
to the contents of registers D0 or D1.
16x ADD.A x+1,D0 ***
17x ADD.A x+1,D1 ***
Examples:
164 ADD 5,D0 ; D0 = D0 + 5 (20 bits)
17E ADD 15,D1 ; D1 = D1 + 15 (20 bits)
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ADD Pointer+1 to Register
809 ADD.A P+1,C
Examples:
809 ADD.A P+1,C ; C = C + P + 1 (20 bits)
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AND
================================================================
AND Register to Register
0Exy AND.f s,d
x | f y | s d
------- ---------
0 | P 0 | B A
1 | WP 1 | C B
2 | XS 2 | A C
3 | X 3 | C D
4 | S 4 | A B
5 | M 5 | B C
6 | B 6 | C A
7 | W 7 | D C
F | A
Examples:
0E63 AND.B C,D ; D = D & C (8 bits)
0EF5 AND.A B,C ; C = C & B (20 bits)
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BRANCH and RETURN
================================================================
These instructions branch or return when an associated test
evaluates true. The destination of the branch is the sum of
an 8 bit sign extended 2's complement offset and the address
of that offset. When the offset is 00, the destination is
reached by popping an address off the return stack.
In the following, the destination argument is expressed relative
to the address of the instruction (designated PC). In the case
of a return, this argument can be omitted and the BR in the
mnemonic substituted with RET.
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Branch/Return Bit Clear
Branch/Return Bit Set
These instructions branch/return depending on whether the
specified bit in a register is 0 or 1.
8086xyy BRBC x,A,PC+5+yy
808Axyy BRBC x,C,PC+5+yy
83zyy BRBC hf,PC+3+yy
86xyy BRBC x,ST,PC+3+yy
8087xyy BRBS x,A,PC+5+yy
808Bxyy BRBS x,C,PC+5+yy
87xyy BRBS x,ST,PC+3+yy
z | hf
--------
1 | XM
2 | SB
4 | SR
8 | MP
Examples:
808B900 RETBS 9,C ; return if bit 9 of C is set
8765F BRBS 6,ST,PC-8 ; jump 8 nibbles before instruction
; if bit 6 of ST is set
8086E02 BRBC 14,A,PC+37 ; jump 37 nibbles from instruction
; if bit 14 of A is clear
83400 RETC SR ; return if Service Request clear
8380F BRBC MP,PC-13 ; jump -13 if Module Pulled clear
________________________________________________________________
Branch/Return Carry Clear
Branch/Return Carry Set
These instructions branch/return depending on whether the
carry flag is clear or set.
5xx BRCC PC+1+xx
4xx BRCS PC+1+xx
Examples:
500 RETCC ; return if carry clear
45F BRCS PC-10 ; branch -10 nibbles if carry set
550 BRCC PC+6 ; branch +6 nibbles if carry clear
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Branch/Return Pointer Equal
Branch/Return Pointer Not Equal
These instructions branch/return depending on whether the
4 bit register P is equal/not equal to a 4 bit constant.
89xyy BREQ.1 P,x,PC+3+yy ***
88xyy BRNE.1 P,x,PC+3+yy ***
Examples:
89C31 BREQ P,12,PC+22 ; branch +22 if P equals 12
88500 RETNE P,5 ; return if P not equal to 5
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Branch/Return Register Inequality
These instructions branch/return depending on the result
of an inequality between the fields of two registers.
ttuyy BREQ.f s,d,PC+3+yy
ttvyy BRNE.f s,d,PC+3+yy
ttwyy BRZ.f s,PC+3+yy
ttxyy BRNZ.f s,PC+3+yy
zzuyy BRGT.f s,d,PC+3+yy
zzvyy BRLT.f s,d,PC+3+yy
zzwyy BRGE.f s,d,PC+3+yy
zzxyy BRLE.f s,d,PC+3+yy
tt zz | f u v w x | s d
----------- ---------------
8A 8B | A 0 4 8 C | A B
90 98 | P 1 5 9 D | B C
91 99 | WP 2 6 A E | C A
92 9A | XS 3 7 B F | D C
93 9B | X
94 9C | S
95 9D | M
96 9E | B
97 9F | W
Examples:
8B500 RETLT.A B,C ; return if B < C (20 bits)
93BD0 BRZ.X D,PC+16 ; branch +16 if D is zero (12 bits)
9FA00 RETGE.W C,A ; return if C >= A (64 bits)
================================================================
BUS COMMANDS
================================================================
8083 BUSCB
80B BUSCC
808D BUSCD
804 UNCNFG ; unconfig all chips
805 CONFIG ; config next chip
806 MOVE.A ID,C ; get ID of current chip
807 SHUTDN ; shutdown bus, stop cpu
80A RESET ; bus reset, resets chips
80E SREQ ; check for service request
================================================================
CALL
================================================================
Call Subroutine Relative
Unlike the BR and relative JUMP commands, relative CALLs
contain an offset from the next instruction. In the
following these are expressed relative to the address of
the CALL instruction itself (PC). Offsets are in stored
in 2's complement form.
7xxx CALL.3 PC+4+xxx ***
8Exxxx CALL.4 PC+6+xxxx
Examples:
7040 CALL PC+68 ; call 68 nibbles from this instruction
8E020E CALL.4 PC-8154 ; call 8154 nibbles back from insruction
________________________________________________________________
Call Subroutine Absolute
8Fxxxxx CALL.A xxxxx
Examples:
8F0200C CALL.A #C0020 ; call to absolute address #C0020h
================================================================
CLEAR
================================================================
Clear Field of Register
ppt CLR.f d
pp | f t| d
-------- ------
A8 | P 0| A
A9 | WP 1| B
AA | XS 2| C
AB | X 3| D
AC | S
AD | M
AE | B
AF | W
D | A
Examples:
D2 CLR.A C ; clear address field of C (20 bits)
A83 CLR.P D ; clear nibble of D pointed to by P
AF0 CLR.W A ; clear all of A (64 bits)
________________________________________________________________
Clear Bit
8084x CLRB x,A
8088x CLRB x,C
84x CLRB x,ST
Examples:
8084D CLRB 13,A ; clear bit 13 of register A
80880 CLRB 0,C ; clear bit 0 of register C
847 CLRB 7,ST ; clear bit 7 of ST
________________________________________________________________
Clear Hardware Status Flag(s)
The bits 1,2,4, and 8 can be ORed together to clear
more than one hardware status flag at a time.
82x CLRB d*
x | d
--------
1 | XM
2 | SB
4 | SR
8 | MP
Examples:
825 CLR XM,SR
822 CLR SB
________________________________________________________________
Clear Bits 0-11 of ST
08 CLR.X ST ***
================================================================
DECREMENT
================================================================
Decrement register one unit. Adjust carry.
0D DEC.1 P ***
kkw DEC.f d
kk | f w | d
-------- -------
A0 | P C | A
A1 | WP D | B
A2 | XS E | C
A3 | X F | D
A4 | S
A5 | M
A6 | B
A7 | W
C | A
Examples:
0D DEC P ; P = P - 1 (4 bits)
A3D DEC.X B ; B = B - 1 (12 bits)
================================================================
IN
================================================================
Copy IN register to register A or C
802 IN.4 A ***
803 IN.4 C ***
================================================================
INCREMENT
================================================================
Increment register one unit. Adjust carry.
0C INC.1 P ***
qqu INC.f d
qq | f u | d
-------- -------
B0 | P 4 | A
B1 | WP 5 | B
B2 | XS 6 | C
B3 | X 7 | D
B4 | S
B5 | M
B6 | B
B7 | W
E | A
Examples:
0C INC P ; P = P - 1 (4 bits)
B77 INC.W D ; D = D - 1 (64 bits)
================================================================
INTERRUPT COMMANDS
================================================================
808F INTOFF
8080 INTON
80810 RSI
================================================================
JUMP
================================================================
JUMP Relative
The JUMP command takes a 2's complement offset relative
to the address of the offset, stored with the least
signficant bit first. In the following, the destination
is expressed relative to the address of the JUMP instruction.
6xxx JUMP.3 PC+1+xxx ***
8Cxxxx JUMP.4 PC+2+xxxx
Examples:
6C10 JUMP PC+29
6C1F JUMP PC-227
8C1001 JUMP.4 PC+4099
________________________________________________________________
Jump Absolute
8Dxxxxx JUMP.A xxxxx
________________________________________________________________
Jump Register Indirect
These opcodes are useful for implementing the threaded
RPL interpreter of the HP28S. They can be expressed
either as MOVE or JUMP instructions. The effect is to
set the PC to the address pointed at by the address
pointed at by the register.
808C JUMP.A @A ***
808C MOVE.A @A,PC ***
808E JUMP.A @C ***
808E MOVE.A @C,PC ***
________________________________________________________________
Jump Register Direct
Opcodes 81B2 and 81B3 can be expressed either as MOVE
or JUMP instructions. The SWAP instructions might be
useful for implementing coroutines.
81B2 JUMP.A A ***
81B2 MOVE.A A,PC ***
81B3 JUMP.A C ***
81B3 MOVE.A C,PC ***
81B6 SWAP.A A,PC ***
81B7 SWAP.A C,PC ***
================================================================
MOVE
================================================================
There are so many MOVE instructions that it might make sense to
distinguish them with their own names, but there is also virtue
in limiting the number of mnemonics one must remember.
________________________________________________________________
MOVE Register to Register
ppz MOVE.f s,d
pp | f z | s d
-------- ---------
A8 | P 4 | B A
A9 | WP 5 | C B
AA | XS 6 | A C
AB | X 7 | C D
AC | S 8 | A B
AD | M 9 | B C
AE | B A | C A
AF | W B | D C
D | A
Examples:
D9 MOVE.A B,C ; C gets B (20 bits)
AE4 MOVE.B B,A ; A gets B (8 bits)
AFB MOVE.W D,C ; C gets D (64 bits)
________________________________________________________________
MOVE Memory to Register
MOVE Register to Memory
These instructions move between memory and registers A
or C by indirecting through address registers D0 or D1.
14x MOVE.A s,d
14y MOVE.B s,d
15xt MOVE.f s,d
15yi MOVE.n s,d ; n = i + 1
x y | s d t | f
-------------- -------
0 8 | A @D0 0 | P
1 9 | A @D1 1 | WP
2 A | @D0 A 2 | XS
3 B | @D1 A 3 | X
4 C | C @D0 4 | S
5 D | C @D1 5 | M
6 E | @D0 C 6 | B
7 F | @D1 C 7 | W
Examples:
142 MOVE.A @D0,A ; A gets 20 bits stored at D0
15D6 MOVE.7 C,@D1 ; Store 28 bits of C at D1
1577 MOVE.W @D1,C ; C gets 64 bits stored at D1
149 MOVE.B A,@D1 ; Store one byte of A at D1
1516 MOVE.B A,@D1 ; Store one byte of A at D1
1591 MOVE.2 A,@D1 ; Store one byte of A at D1
________________________________________________________________
MOVE Register to Address Register
13w MOVE.A s,Da ***
13y MOVE.4 s,Da
w y | s Da
-----------
0 8 | A D0
1 9 | A D1
4 C | C D0
5 D | C D1
Examples:
131 MOVE A,D1 ; D1 gets A (20 bits)
13C MOVE.4 C,D0 ; D0 gets C (16 bits)
________________________________________________________________
MOVE Register to Temporary Register
MOVE Temporary Register to Register
10j MOVE.W A,Rn ***
10k MOVE.W C,Rn ***
11j MOVE.W Rn,A ***
11k MOVE.W Rn,C ***
81At0j MOVE.f A,Rn
81At0k MOVE.f C,Rn
81At1j MOVE.f Rn,A
81At1k MOVE.f Rn,C
81At2j SWAP.f A,Rn
81At2k SWAP.f C,Rn
t | f j k | Rn
------- ----------
0 | P 0 8 | R0
1 | WP 1 9 | R1
2 | XS 2 A | R2
3 | X 3 B | R3
4 | S 4 C | R4
5 | M
6 | B
7 | W
F | A
Examples:
100 MOVE A,R0 ; R0 gets A (64 bits)
11C MOVE R4,C ; C gets R4 (64 bits)
81A71C MOVE.W R4,C ; C gets R4 (64 bits)
81A309 MOVE.X C,R1 ; R1 gets C (12 bits)
________________________________________________________________
MOVE Register to PC
MOVE PC to Register
Opcodes 81B2 and 81B3 can be expressed either as MOVE
or JUMP instructions.
81B2 MOVE.A A,PC ***
81B3 MOVE.A C,PC ***
81B4 MOVE.A PC,A ***
81B5 MOVE.A PC,C ***
________________________________________________________________
MOVE Register Indirect to PC
These opcodes are useful for implementing the threaded
RPL interpreter of the HP28S. They can be expressed
either as MOVE or JUMP instructions. The effect is to
set the PC to the address pointed at by the address
pointed at by the register.
808C MOVE.A @A,PC ***
808E MOVE.A @C,PC ***
________________________________________________________________
MOVE Constant to Register
These instructions move a variable length constant from
the instruction stream into registers A or C beginning
with the nibble pointed to by register P. This results
in a unique field type, Pn, where P designates the position
where the constant will be moved and n the size of the
constant in nibbles.
3ix...x MOVE.Pn x...x,C ; n = i + 1
8082ix...x MOVE.Pn x...x,A ; n = i + 1
Examples:
34910C0 MOVE.P5 #C019,C
32310 MOVE.P3 19,C
808234000 MOVE.P4 4,A
________________________________________________________________
MOVE Constant to Address Register
19xx MOVE.2 xx,D0
1Axxxx MOVE.4 xxxx,D0
1Bxxxxx MOVE.5 xxxxx,D0
1Dxx MOVE.2 xx,D1
1Exxxx MOVE.4 xxxx,D1
1Fxxxxx MOVE.5 xxxxx,D1
Examples:
1940 MOVE.2 4,D0 ; D0 gets 4 (8 bits)
1E1234 MOVE.4 #4321,D1 ; D1 get #4321h (16 bits)
1B12340 MOVE.5 #4321,D0 ; D0 gets #04321h (20 bits)
________________________________________________________________
MOVE Constant to Pointer Register
2x MOVE.1 x,P ***
Examples:
27 MOVE 7,P ; P points to nibble 7
2C MOVE 12,P ; P points to nibble 12
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MOVE Pointer Register to Register Nibble
MOVE Register Nibble to Pointer Register
Move 4 bit P register value to or from the specified
nibble (x) of regiester C.
80Cx MOVE.1 P,C,x ***
80Dx MOVE.1 C,x,P ***
Examples:
80C0 MOVE P,C,0 ; nibble 0 of C gets P (4 bits)
80D7 MOVE C,7,P ; P gets nibble 7 of C (4 bits)
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MOVE Register to Status Register
MOVE Status Register to Register
09 MOVE.X ST,C ***
0A MOVE.X C,ST ***
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NEGATE
================================================================
Negate Register (2's complement)
rrv NEG.f d
rr | f v | d
-------- -------
B8 | P 8 | A
B9 | WP 9 | B
BA | XS A | C
BB | X B | D
BC | S
BD | M
BE | B
BF | W
F | A
Examples:
FA NEG.A C ; C = -C (20 bits)
BEB NEG.B D ; D = -D (8 bits)
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NO OPERATION
================================================================
NOP
These instructions do nothing.
420 NOP3
6300 NOP4
64000 NOP5
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NOT
================================================================
Invert Register (1's complement)
rrw NOT.f d
rr | f w | d
-------- -------
B8 | P C | A
B9 | WP D | B
BA | XS E | C
BB | X F | D
BC | S
BD | M
BE | B
BF | W
F | A
Examples:
BCE NOT.S C ; invert nibble 15 of C (4 bits)
FF NOT.A D ; invert D (20 bits)
================================================================
OR
================================================================
OR Register to Register
0Exz OR.f s,d
x | f z | s d
------- ---------
0 | P 8 | B A
1 | WP 9 | C B
2 | XS A | A C
3 | X B | C D
4 | S C | A B
5 | M D | B C
6 | B E | C A
7 | W F | D C
F | A
Examples:
0E6C OR.B A,B ; B = B & A (8 bits)
0EFF OR.A D,C ; C = C & D (20 bits)
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OUT
================================================================
Copy OUT register to register A or C
800 OUT.S C
801 OUT.X C
================================================================
POP
================================================================
POP Address from Stack
07 POP.A C ***
================================================================
PUSH
================================================================
PUSH Address onto Stack
06 PUSH.A C ***
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RETURN
================================================================
Return from Subroutine, popping return address from stack
01 RET ; return
02 RETSETC ; set carry and return
03 RETCLRC ; clear carry and return
0F RETI ; enable int and return
00 RETSETXM ; set XM flag and return
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Conditional Return
See BRANCH. Branch instructions function as conditional
returns when their destination offset is zero.
================================================================
ROTATE
================================================================
Rotate Left nibble
Rotate Right nibble
The SB flag is set when a non-zero nibble is shifted
from postion 0 to 15 (RRN only).
81w RLN.W d
81x RRN.W d
w x | d
---------
0 4 | A
1 5 | B
2 6 | C
3 7 | D
Examples:
810 RLN.W A ; rotate A one nibble left
816 RRN.W C ; rotate C one nibble right
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SET
================================================================
Set Bit
8085x SETB x,A
8089x SETB x,C
85x SETB x,ST
Examples:
8085D SETB 13,A ; clear bit 13 of register A
80890 SETB 0,C ; clear bit 0 of register C
857 SETB 7,ST ; clear bit 7 of ST
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Set Decimal
Set Hexadecimal
Sets the CPU to do register arithmetic in HEX (binary) or
DEC (binary coded decimal) mode.
05 SETDEC
04 SETHEX
================================================================
SHIFT
================================================================
Shift Left nibble
Shift Right nibble
Shift Right Bit
The SB flag is set when a non-zero nibble/bit is shifted
out of position 0 (SRN/SRB only). Zeros shifted in.
rrw SLN.f d
rrx SRN.f d
819tw SRB.f d
81z SRB.W d
rr t | f w x z | d
----------- -----------
B8 0 | P 0 4 C | A
B9 1 | WP 1 5 D | B
BA 2 | XS 2 6 E | C
BB 3 | X 3 7 F | D
BC 4 | S
BD 5 | M
BE 6 | B
BF 7 | W
F F | A
Examples:
F3 SLN.A D ; shift D left one nibble (20 bits)
BE6 SRN.B C ; shift C right one nibble (8 bits)
81931 SRB.X B ; shift B right one bit (12 bits)
================================================================
SUB
================================================================
Subtract Register from Register
The SUBN instruction stores the negative of the
subtraction in the destination.
qqy SUB.f s,d
qqw SUBN.f s,d
qq | f y w | s d
-------- -----------
B0 | P 0 C | B A
B1 | WP 1 D | C B
B2 | XS 2 E | A C
B3 | X 3 F | C D
B4 | S 8 | A B
B5 | M 9 | B C
B6 | B A | C A
B7 | W B | D C
E | A
Examples:
E2 SUB.A A,C ; C = C - A (20 bits)
EE SUBN.A A,C ; C = - (C - A) = A - C (20 bits)
B70 SUB.W B,A ; A = A - B (64 bits)
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Subtract Constant from Register
"The 818... opcodes don't always work as advertised.
To be specific, when the field of such an instruction
is XS, S, P, or WP, and a carry (or borrow) is generated
out of the most significant nibble, it wraps around and
affects the least significant nibble." -- D.K.
818tyi SUB.f i+1,d
t | f y | d
------- -------
0 | P 8 | A
1 | WP 9 | B
2 | XS A | C
3 | X B | D
4 | S
5 | M
6 | B
7 | W
F | A
Examples:
818594 SUB.M 5,B ; B = B - 5 (48 bits)
8186BD SUB.B 14,D ; D = D - 14 (8 bits)
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Subtract Constant from Address Register
18x SUB.A x+1,D0 ***
1Cx SUB.A x+1,D1 ***
Examples:
184 SUB 5,D0 ; D0 = D0 - 5 (20 bits)
1C9 SUB 10,D1 ; D1 = D1 - 10 (20 bits)
================================================================
SWAP
================================================================
SWAP Register with Register
ppw SWAP.f s,d
pp | f w | s d
-------- ---------
A8 | P C | B A
A9 | WP D | C B
AA | XS E | A C
AB | X F | C D
AC | S
AD | M
AE | B
AF | W
D | A
Examples:
DF SWAP.A C,D ; interchange values of C and D
ABC SWAP.X A,B ; interchange low 3 nibbles of A and B
________________________________________________________________
SWAP Register with Address Register
13x SWAP.A s,Da ***
13z SWAP.4 s,Da
x z | s Da
------------
2 A | A D0
3 B | A D1
6 E | C D0
7 F | C D1
Examples:
137 SWAP C,D1 ; interchange low 20 bits of C and D1
13A SWAP.4 A,D0 ; interchange low 16 bits of A and D0
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SWAP Register with Temporary Register
12j SWAP.W A,Rn ***
12k SWAP.W C,Rn ***
81At2j SWAP.f A,Rn
81At2k SWAP.f C,Rn
t | f j k | Rn
------- ----------
0 | P 0 8 | R0
1 | WP 1 9 | R1
2 | XS 2 A | R2
3 | X 3 B | R3
4 | S 4 C | R4
5 | M
6 | B
7 | W
F | A
Examples:
121 SWAP A,R1 ; interchange A with R1 (64 bits)
12B SWAP C,R3 ; interchange C with R3 (64 bits)
81AF24 SWAP.A A,R4 ; interchange A with R4 (20 bits)
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SWAP Register with PC
These operations have the effect of saving the PC of
the next instruction and transferring control to the
address contained in the register. This can be useful
for implementing coroutines.
81B6 SWAP.A A,PC ***
81B7 SWAP.A C,PC ***
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SWAP Register with Pointer Register
Swap 4 bit P register value with the high order nibble
of the specified field of register C.
80Fx SWAP.1 P,C,x ***
Examples:
80F0 SWAP P,C,0 ; interchange P with low nibble of C
80FF SWAP P,C,15 ; interchange P with high nibble of C
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SWAP Register with Status Register
0B SWAP.X C,ST ***
================================================================
