tCFGCYRIX

 CfgCyrix  version 1.0  Copyright (C) 1992 Tom Warren/TechGuys SW 

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Usage: DEVICE=CFGCYRIX.SYS /A0 /B0 /C0 /D0 /E1 /F1 /H0 /K0 /R0 /S0 

[the above command line works well on a 386DX/33 mainboard with a Cx486DLC/33]


A0 = A20M# input pin (A20 mask) disabled, A1 = enabled 

B0 = BARB (flush on HOLD) disabled, B1 = enabled 

C0 = 2-way set-associative cache, C1 = direct-mapped cache 

D0 = Debug flag disabled, D1 = enabled (verbose initialization info) 

E0 = mark 640K-1Meg region as cacheable, E1 = mark region as noncacheable (NC0)

F0 = FLUSH# input pin (cache flush) disabled, F1 = flush enabled 

H0 = set first 64K of each 1Meg boundary cacheable (real/V86 mode),

     H1 = set first 64K of each 1Meg boundary noncacheable (NC1) 

K0 = KEN# input pin (cache enable) disabled,K1 = cache enabled 

R0 = RPLSET/RPLVAL# output pins disabled (floated), R1 = enabled 

S0 = SUSP# input/SUSPA# output pins disabledS1 = enabled 


 Note that the Cyrix 486xLC resets all bits to 0 at power-on. 

 You can specify just the bits that you want set (typically, /E1 /F1) 


 Tom Warren, Moorpark, CA  - [CompuServe 76167,1572] 

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 Cyrix Cx486SLC/DLC not detected - aborting! 

$

 WARNING: Cyrix Cache Config Reg 0 is not = 00 at initialization! 

 Another program/BIOS may have already modified it! 

$

 Writing 0000 to Cyrix CC0 (Cache Config Reg 0) 

$ Request Header address at load time: 0000:0000

$ A20M# input pin (A20 mask) =  

$ BARB (flush on HOLD) =  

$ C0 (Cache Orginization, 0 = 2-way set-associative, 1 = direct-mapped) =  

$ Debug flag =  

$ NC1 (set 640K-1Meg region noncacheable) =  

$ FLUSH# input pin (cache flush) =  

$ NC0 (set first 64K of each 1Meg boundary noncacheable, real/V86 mode) =  

$ KEN# input pin (cache enable) =  

$ RPLSET/RPLVAL# output pins (1 = enabled) =  

$ SUSP# input/SUSPA# output pin enable =  

$ Unknown argument:  

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