NCR 77C21 NCR 77C22 NCR 77C22E 4MB, 1280x1024 256 col NCR 77C22E+ NCR 77C22BLT BitBLT support 3C4h index 5 (R/W): Extended Function Enable Register bit 0 Enables extended registers if set. 1 Reserved (always 0). 2 If set the Hardware Configuration registers (3C4h index 23h bit 0-3, index 27h bit 1, index 1Fh bit 5 and index 1Eh bits 0-1) can be modified. 3-7 Reserved 3C4h index 8 (R): Version Number Register bit 0-3 Chip revision 4-7 Product Code: 0=77C22, 1=77C21, 2=77C22E and >=8 is 77C22E+. 3C4h index 0Ah (R/W): Cursor Foreground Color Register bit 0-7 Foreground color of the Bit Mapped Cursor. Plane 0=0 and plane 1=1. 3C4h index 0Bh (R/W): Cursor Background Color Register bit 0-7 Background color of the Bit Mapped Cursor. Plane 0=0 and plane 1=0. 3C4h index 0Ch (R/W): Cursor Control Register bit 0 Cursor enable. When set enables the Bit Mapped cursor. 1-2 Cursor height select. 0=16 lines, 1=32 lines, 2=64 lines and 3=128 lines. 3 Blink frequency select. If set the Bit Mapped Cursor is on for 16 frames and off for another 16 frames. If clear it is on for 8 frames and off for another 8 frames. 4 If set the Bit Mapped Cursor blinks. 5-7 Reserved. 3C4h index 0Dh (R/W): Cursor X Location High register bit 0-2 Bits 8-10 of the horizontal position of the Bitmapped Cursor. The lower 8 bits are in 3C4h index 0Eh. 3-7 Reserved 3C4h index 0Eh (R/W): Cursor X Location Low register bit 0-7 Lower 8 bits of the horizontal position of the Bitmapped Cursor. The upper 3 bits are in 3C4h index 0Dh. 3C4h index 0Fh (R/W): Cursor Y Location High register bit 0-1 Bits 8-9 of the vertical position of the Bitmapped Cursor. The lower 8 bits are in 3C4h index 10h. 2-7 Reserved 3C4h index 10h (R/W): Cursor Y Location Low register bit 0-7 Lower 8 bits of the vertical position of the Bitmapped Cursor. The upper 2 bits are in 3C4h index 0Fh. 3C4h index 11h (R/W): Cursor X Index Register. bit 0-5 Horizontal location of the Hot Spot from the left of the cursor. 6-7 Reserved. 3C4h index 12h (R/W): Cursor Y Index Register. bit 0-4 Vertical location of the Hot Spot from the top of the cursor. 5-7 Reserved. 3C4h index 13h (R/W): Cursor Storage Register High. bit 0-7 Bits 8-15 of the address of the cursor bitmap. The lower 8 bits are in 3C4h index 14h. 3C4h index 14h (R/W): Cursor Storage Register Low. bit 0-7 Bits 0-7 of the address of the cursor bitmap. The upper 8 bits are in 3C4h index 13h. 3C4h index 15h (R/W): Cursor Storage Offset Register High. bit 0-7 Bits 8-15 of the Cursor Storage Offset. The lower 8 bits are in 3C4h index 16h. 3C4h index 16h (R/W): Cursor Storage Offset Register Low. bit 0-7 Bits 0-7 of the Cursor Storage Offset. The upper 8 bits are in 3C4h index 15h. If extended memory is enabled (3C4h index 1Eh bit4 set) the Cursor Storage Offset is multiplied with 16 and added to the Cursor Storage Address to form a 20 bit address. Note: The cursor map is stored as a #lines*(32+32bit) bitmap The behavior of the cursor in each pixel is defined by the combination of the pixels from the two 32bit maps (The first pixel of the cursor is stored in the last byte): 1st 2nd Description 0 0 Background color (index 0Bh) 0 1 Foreground color (index 0Ah) 1 0 screen data (transparent cursor) 1 1 Inverted screen data (XOR cursor) Note: It is possible that for the 77c22e revision 2 the pixel order in the map should be reversed. 3C4h index 17h (R/W): Cursor Pixel Mask Register. bit 0-7 Each bit set allows the corresponding bit in a pixel to be affected by the Bitmapped Cursor. 3C4h index 18h (R/W): Primary Host Offset Register High. bit 0-7 Bits 8-15 of the Primary Host Offset. The lower 8 bits are in 3C4h index 19h. 3C4h index 19h (R/W): Primary Host Offset Register Low. bit 0-7 Bits 0-7 of the Primary Host Offset. The upper 8 bits are in 3C4h index 18h. If extended memory is enabled (3C4h index 1Eh bit4 is set) all Host addresses are modified by multiplying either the Primary or the Secondary Host Offset with 16 and adding the result to the Host address. If 3C4h index 1Eh bit is set all read operations use the Secondary Host Offset and all write operations use the Primary Host address, otherwise both read and write operations use the Primary Host Offset. 3C4h index 1Ah (R/W): Display Offset Register High. bit 0-7 Bits 8-15 of the Display Offset. The lower 8 bits are in 3C4h index 1Bh. 3C4h index 1Bh (R/W): Display Offset Register Low. bit 0-7 Bits 0-7 of the Display Offset. The upper 8 bits are in 3C4h index 1Ah. If extended memory and Display Offset are enabled (3C4h index 1Eh bit4 and 3 are both set) the Display Offset is multiplied with 16 and added to the normal display address. 3C4h index 1Ch (R/W): Secondary Host Offset Register High. bit 0-7 Bits 8-15 of the Secondary Host Offset. The lower 8 bits are in 3C4h index 1Dh. 3C4h index 1Dh (R/W): Secondary Host Offset Register Low. bit 0-7 Bits 0-7 of the Secondary Host Offset. The upper 8 bits are in 3C4h index 1Ch. If extended memory and Secondary Offset are enabled (3C4h index 1Eh bit4 and 2 are both set) all read operations are modified by multiplying the Secondary Offset by 16 and adding the result to the Host address. 3C4h index 1Eh (R/W): Extended Memory Enable Register. bit 0-1 DRAM configuration. These bits can only be modified if 3C4h index 5 bit 2 is set. 2 If this bit and bit 4 are set all read operations are modified by multiplying the Secondary Host Offset by 16 and adding the result to the host address. 3 If this bit and bit 4 are set all display addresses are modified by multiplying the Display Offset by 16 and adding the result to the normal display address. 4 If set extended memory is enabled. 5-7 Reserved. 3C4h index 1Fh (R/W): Extended Clocking Mode. bit 0-3 If bit 4 set this determines the font width: 0 4 bit wide font 1 7 bit wide font 2 8 bit wide font 3 9 bit wide font 4 10 bit wide font 5 11 bit wide font 6 12 bit wide font 7 13 bit wide font 8 14 bit wide font 9 15 bit wide font 0Bh 16 bit wide font 4 If set enables extended font width. 5 Clock Output enable. 6 (22E,22E+) Clock Select Bit 2 7 Reserved 3C4h index 20h (R/W): Extended Video Memory Addressing Register bit 0 Addition of host address bit 16. 1 Extended chain-4 enable. 2-7 Reserved. 3C4h index 21h (R/W): Extended Pixel Control Register bit 0 Enable graphics byte path if set. 1 Enable packed/nibble pixel format (2 pixels of 4 bits per byte) if set. 2-7 Reserved. 3C4h index 22h (R/W): Bus Width Feed Back Register. bit 0 Enables 16 bit memory access if set. 1 Enables 16 bit I/O access if set. 2-7 Reserved. 3C4h index 23h (R/W): Performance Select Register bit 0 Reserved (Burst Enable). 1 Selects 3 clock RAS cycles if set. Should not be set!! 2 Enables Fast Page Mode if set. Set by external resistor. 3-5 Reserved. 6 Unlatched Memory Writes (Only in 256 color modes with OSC3). If set limits the duration of CHRDY assertion time by limiting FIFO fill lengths. 7 Latched Memory Reads. If set the assertion of CHRDY can be eliminated during read cycles. 3C4h index 24h (R/W): Color Expanded Write Foreground Register. bit 0-7 When in expanded write mode (3C4h index 26h bit 0 set) a monochrome bitmap can be expanded to 256 or 16 colors 8 or 16 pixels at a time. '1' bits in the bitmap are expanded to this color. For 16 color modes only bit 0-3 are used. 3C4h index 25h (R/W): Color Expanded Write Background Register. bit 0-7 When in expanded write mode (3C4h index 26h bit 0 set) a monochrome bitmap can be expanded to 256 or 16 colors 8 or 16 pixels at a time. '0' bits in the bitmap are expanded to this color. For 16 color modes only bit 0-3 are used. 3C4h index 26h (R/W): Extended Read/Write Control Register. bit 0 FG/BG Color Expansion Enable. When set enables expansion from monochrome bitmaps to full color using 3C4h index 24h and 25h as fore- and background colors. 1 Color Expansion Enable Mode 1 If set enables 256 color expansion. If clear 8bit pixel values can be written to the framebuffer as in standard mode 13h. If clear and bit 0 is set then 16 color expansion is enabled. 2 Color Expansion Enable Mode 2. If set accesses to even addresses will work on the upper 4 bits of the data at the even address and the lower 4 bits of the data at the following odd address. This mode should only be used when the 77C22E is configured as a 16 bit device and only with even addresses. 3 Planar to Packed Pixel Conversion Enable Enables 16/256 color pixel expansion when set. This bit should always be set when bit 1 is. 4 Packed Pixel Mask Enable When in packed pixel modes, this bit is set to enable pixel masking operations. This bit should be set when bit 1 is. 5 Packed Pixel Color Compare When set configures the color compare logic to operate on packed pixel data. This bit should be set when bit 1 is. 6 Quad Word Read Latch for Writes If set 64 bits are written when 16 bit latched write operations occurs in write mode 1. Allows fast copy of data within the framebuffer. 7 Address Toggle When bit 6 is set this bit specifies how address information is maintained with the latched data. 3C4h index 27h (R/W): Miscellaneous Feature Select Register. bit 0 Extended Palette addressing enable. If set I/O address bit 15 is passed to the RS2 pin of the palette DAC chip, so that I/O address 03C6h - 03C9h address the first 4 registers of the DAC chip and 83C6h - 83C9h address four other registers. Useful for advanced DACs with overlay and command registers. 1 If set the 77C22E outputs DRAM interface signals for direct interfacing with 64K x 16 DRAMS. 2 If set this bit disables the address decoding for the BIOS ROM at C000h-C7FFFh thus allowing this area to be used for other adapters. 3 User Defined Output (I/O Control pin 2). This bit is output on pin 2 for clock control. 3d4h index 30h (R/W): Extended Horizontal Timings Register. bit 0 Horizontal Total bit 8. Bit 8 of the Horizontal Total register. Bits 0-7 are in 3d4h index 4. 1 Horizontal Display Enable End bit 8. Bit 8 of the Horizontal Display Enable End register. Bits 0-7 are in 3d4h index 2. 2 Start Horizontal Blanking bit 8. Bit 8 of the Start Horizontal Blanking register. Bits 0-7 are in 3d4h index 1. 3 Start Horizontal Retrace bit 8. Bit 8 of the Start Horizontal Retrace register. Bits 0-7 are in 3d4h index 0. 4 (22E, 22E+) Interlace Enable. Enables interlace video for high resolution graphics modes. Note in interlaced modes the line doubling from index 9 bits 0-4&7 is ignored. 5-7 Reserved. Note: The extended Function Enable Register (3C4h index 5) bit 0 must be 1 to access this register. 3d4h index 31h (R/W): Extended Start Address Register bit 0-3 Display Start Address bit 16-19. (bit 0-15 are in 3d4h index Ch and Dh). 4-7 Reserved. ID NCR VGA: if testinx2($3C4,5,5) then begin wrinx($3C4,5,0); {Lock extensions} if not testinx($3C4,$10) then begin wrinx($3C4,5,1); if testinx($3C4,$10) then case rdinx($3C4,8) div 16 of 0:NCR 77C22; 1:NCR 77C21; 2:NCR 77C22E; 8..15:NCR 77C22E+; end; end; end; Video Modes: 54h T 132 50 16 (8x8) 55h T 132 25 16 (8x16) 56h T 132 50 4 (8x8) 57h T 132 25 4 (8x16) 58h G 800 600 16 PL4 59h G 800 600 2 5Ah G 1024 768 2 5Bh G 1024 768 16 PL4 (Interlaced) 5Ch G 800 600 256 P8 5Dh G 1024 768 16 PL4 5Eh G 640 400 256 P8 5Fh G 640 480 256 P 61h G 1024 768 256 P8 (Interlaced) 22E !! 62h G 1024 768 256 P8 22E !! 67h G 1280 1024 16 PL4 (Interlaced) 22E !! 6Ah G 1280 1024 256 P8 (Interlaced) 22E !! 6Bh G 1280 960 256 P8 22E !! 70h G 640 480 32k P15 22E !! 71h G 800 600 32k P15 22E 78h G 640 480 64k P16 22E 79h G 800 600 64k P16 22E Note: Modes above 57h may require a driver (setmode.sys) to be loaded depending on BIOS version.