ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ From : Inbar Raz Port Description ßßßß ßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßß 000H-01fH DMA (Direct Memory Access) controller See DMA Ports 020H-03fH Interrupt Controller ============================================================================== DMA (Direct Memory Access) is used for high-speed data transfers between I/O devices and memory without intervention of the CPU. It is typically employed by diskette and hard disk drivers, but it could be used for streaming tape or any other device as long as it does not interfere with the operation of other standard devices. The original PC supports four 8-bit DMA channels, across a 20-bit address space, using an Intel 8237A DMA controller chip. The ÝATÞ supports 7 DMA channels by cascading a second 8237A DMA controller. The differences between PC and AT DMA are covered at the end of this section. Channel Usage in PC and XT ßßßßßßß ßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßß 0 memory refresh (highest priority) 1 not used 2 diskette adapter 3 hard disk adapter (lowest priority) Port Description ßßßß ßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßß 000H-007H DMA base address an offset registers All are 16-bit registers: read/write the low byte, then the high byte at the same I/O port. Base addresses are offsets from a DMA Page (see below). 000H Write: DMA channel 0 base address (also sets current address) Read: DMA channel 0 current address 001H Write: DMA channel 0 base address and word count Read: DMA channel 0 current word count 002H Write: DMA channel 1 base address Read: DMA channel 1 current address 003H Write: DMA channel 1 base address and word count Read: DMA channel 1 current word count 004H Write: DMA channel 2 base address (diskette adapter) Read: DMA channel 2 current address " 005H Write: DMA channel 2 base address and word count " Read: DMA channel 2 current word count " 006H Write: DMA channel 3 base address (hard disk adapter) Read: DMA channel 3 current address " 007H Write: DMA channel 3 base address and word count " Read: DMA channel 3 current word count " þþþþ þþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþ 008H-00fH DMA control/status registers 008H Write: DMA command register Ö7Â6Â5Â4Â3Â2Â1Â0· º ³ ³ ³ ³ ³ ³ ³ º ÓÒÁÒÁÒÁÒÁÒÁÒÁÒÁÒ½ bit º º º º º º º ÈÍ 0: 1=enable memory-to-memory DMA (ch0Ích1) º º º º º º ÈÍÍÍ 1: 1=enable Ch0 address hold º º º º º ÈÍÍÍÍÍ 2: 1=disable controller º º º º ÈÍÍÍÍÍÍÍ 3: 1=select compressed timing mode º º º ÈÍÍÍÍÍÍÍÍÍ 4: 1=enable rotating priority º º ÈÍÍÍÍÍÍÍÍÍÍÍ 5: 1=select extended write mode; 0=late write º ÈÍÍÍÍÍÍÍÍÍÍÍÍÍ 6: 1=select DRQ sensing as active high; 0=low ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ 7: 1=select DACK sensing as active high; 0=low Read: DMA status register Ö7Â6Â5Â4Â3Â2Â1Â0· º ³ ³ ³ ³ ³ ³ ³ º ÓÄÁÄÁÄÁÄÁÄÁÄÁÄÁĽ bit ÈÍÍËÍͼ ÈÍÍÍÍÍÊÍ 0-3: channel 0-3 has reached terminal count ÈÍÍÍÍÍÍÍÍÍÍÍÍ 4-7: channel 0-3 has a request pending 009H Write: request register Ö7Â6Â5Â4Â3Â2Â1Â0· º unused ³ ³ º ÓÄÁÄÁÄÁÄÁÄÁÒÁÄÁĽ bit º ÈÍÊÍ 0-1: select channel (00=0; 01=1; 10=2; 11=3) ÈÍÍÍÍÍ 2: 1=set request bit for channel; 0=reset request 00aH Write: single mask bit register Ö7Â6Â5Â4Â3Â2Â1Â0· º unused ³ ³ º ÓÄÁÄÁÄÁÄÁÄÁÒÁÄÁĽ bit º ÈÍÊÍ 0-1: select channel (00=0; 01=1; 10=2; 11=3) ÈÍÍÍÍÍ 2: 1=set mask for channel; 0=clear mask (enable) 00bH Write: mode register Ö7Â6Â5Â4Â3Â2Â1Â0· º ³ ³ ³ ³ ³ ³ ³ º ÓÄÁÄÁÒÁÒÁÄÁÄÁÄÁĽ bit È˼ º º È˼ ÈÍÊÍ 0-1: select channel (00=0; 01=1; 10=2; 11=3) º º º ÈÍÍÍÍÍÍ 2-3: transfer type (00=verify=Nop; 01=write; 10=read) º º ÈÍÍÍÍÍÍÍÍÍ 4: 1=enable auto-initialization º ÈÍÍÍÍÍÍÍÍÍÍÍ 5: 1=select address increment; 0=address decrement ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍ 6-7: 00=demand mode; 01=single; 10=block; 11=cascade 00cH Write: clear byte pointer flip-flop. Any write clears the flip-flop so that the next write to any of the 16-bit registers is decoded as the low byte. The next is the high byte, then next is low, etc. 00dH Write: master clear. Any OUT clears the ctrlr (must be re-initialized) Read: temporary reg. Last byte in memory-to-memory xfer (not used) 00eH Write: Clear mask registers. Any OUT enables all 4 channels. 00fH Write: master clear. Clear or mask any or all of the channels. Ö7Â6Â5Â4Â3Â2Â1Â0· º ³ ³ ³ ³ º ÓÄÁÄÁÄÁÄÁÒÁÒÁÒÁÒ½ bit º º º ÈÍ 0: 1=mask channel 0; 0=enable º º ÈÍÍÍ 1: 1=mask channel 1; º ÈÍÍÍÍÍ 2: 1=mask channel 2; ÈÍÍÍÍÍÍÍ 3: 1=mask channel 3; Read: temporary reg. Last byte in memory-to-memory xfer (not used) þþþþ þþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþ 081H-08fH DMA page registers. To select a starting address for a DMA operation, do an OUT to the page register (ports 81H-83H) for the selected channel then set the base address (ports 00H-07H) for the channel. A page register is set with a 4-bit value that represents bits 16-19 of the 20-bit DMA address. Since the current address is a 16-bit value, it is not possible to cross a 64K boundary (eg, address 1000:0, 2000:0, etc.) with a DMA operation. 081H Channel 2 page register (diskette DMA) 082H Channel 3 page register (hard disk DMA) 083H Channel 1 page register ßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßß ÚÄÄÄÄÄÄÄÄÄ¿ ³ÝATÞ DMA ³ The DMA system on the AT is basically upwardly-compatible with PC ÀÄÄÄÄÄÄÄÄÄÙ and XT DMA. In addition to the four 8-bit channels of the PC, the AT adds a second 8237A-5 DMA controller which supports channels 4-7. Channel Usage in AT ßßßßßßß ßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßß 0 spare Ä¿ 1 SDLC (Synchronous Data Link Control) ÆÍ 8-bit DMA channels 2 diskette adapter ³ ³ 3 hard disk adapter ÄÙ ³ 4 (controller 2) cascade for controller 1 Ä¿ ³ 5 spare ÆÍ 16-bit DMA channels ³ 6 spare ³ ³ 7 spare ÄÙ ³ ³ þþþþ þþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþ³ 081H-08fH DMA page registers. On the AT, all 8 bits of the Page registers are³ used. They become the high 8-bits of a 24-bit address space (with the ³ low 16-bits being set in a channel's base/current address register). ³ The page size is 128K (64K words) so DMA transfers must not cross a 128K³ boundary (eg, address 2000:0, 4000:0, 6000:0, etc.) ³ ³ 081H Channel 2 page register (diskette DMA) (address bits 16-23) ³ 082H Channel 3 page register (hard disk DMA) (address bits 16-23) ³ 083H Channel 1 page register (address bits 16-23) ³ 087H Channel 0 page register (address bits 16-23) ³ 089H Channel 6 page register (address bits 17-23) ³ 08bH Channel 5 page register (address bits 17-23) ³ 08aH Channel 7 page register (address bits 17-23) ³ 0ceH Channel 7 current word count þþþþ þþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþ 0d0H-0dfH ÝATÞ DMA control/status registers =================================================================== Inbar Raz