LXT-200A
Product Specification
and OEM Technical Manual
Document 1019708
Revision A
October 1989
REVISION RECORD
Revision Date Published Revised Contents
A October 1989 Formal Release
Document No: 1019708
WARRANTY
Maxtor warrants the LXT-200Aª Family of disk drives against
defects in materials and workmanship for a period of twelve
months, for the original purchaser. Direct any questions
regarding the warranty to your Maxtor Sales Representative.
Maxtor maintains Customer Service Centers for the repair and
reconditioning of all Maxtor products. Direct all requests
for repair to the Maxtor Service Center in San Jose. This
assures you of the fastest possible service.
REGULATORY APPROVALS
UL Recognition: File Number E87276
CSA Certification: File Number LR87443-1
TUV Certification: File Number R98179
Address comments concerning this manual to:
Maxtor Corporation
Technical Publications
211 River Oaks Parkway
San Jose, California 95134-1913
Telephone: (408) 432-1700
Telex: 171074
FAX: (408) 434-6469
Technical Data Restrictions
In case of sale to or use of units by DoD: Use, duplication or
disclosure of any software, firmware or related documentation
is subject to restrictions stated in paragraph (c) (1) (ii) of
the Rights in Technical Data and Computer Software clause at
DFAR 252.227-7013. For Civilian Agencies: Use, reproduction,
or disclosure of the software and related documentation is
subject to restrictions set forth in FAR 52.227-19.
Unpublished rights reserved under the copyright laws of the
United States. Maxtor Corporation, 211 River Oaks Parkway,
San Jose, CA 95134.
Copyright Notice
This manual and all material contained in it are copyrighted.
The manual may not be copied, in whole or in part, without the
written consent of Maxtor Corporation. The contents of this
manual may be revised without prior notice.
© Copyright 1989 by Maxtor Corporation, San Jose, California,
USA. All rights reserved
PREFACE
The purpose of this manual is to provide all of the technical
information you need to install and use the Maxtor LXT-200A
Family of disk drives. It is intended for evaluation and
integration Engineers who are building or assembling a total
computer system. This manual does not include the information
needed to repair these drives. For this information contact
the Maxtor Service Center in San Jose.
Chapter 1 is a complete description of the drive, including
specifications. Chapter 2 provides the information you need
to prepare the drive for installation. Chapter 3 covers
installation. Chapter 4 provides information on the physical
interface of the drive. Chapter 5 covers the ATA register
set. Chapter 6 covers the ATA command set.
Maxtor publishes descriptive brochures and data sheets, this
technical manual, and a quick reference guide for each product
line. Changes that affect the content of any manual are
covered by addenda or revisions to the affected manual.
Maxtor reserves the right to make changes and/or improvements
to its products without incurring any obligation to
incorporate such changes or improvements in units previously
sold or shipped.
LXT-200A Product Specification & OEM Technical Manual
TABLE OF CONTENTS
LXT-200A Product Specification & OEM Technical Manual
TABLE OF CONTENTS
PREFACE.....................................................V
1.0....................................DISK DRIVE DESCRIPTION
1
1.1.............................Drive Features and Benefits
2
1.2..................................Product Specifications
4
1.2.1.........................Performance Specifications
4
1.2.2..........................Functional Specifications
5
1.2.3.......................Environmental Specifications
6
1.2.4............................Physical Specifications
7
1.2.5.........................Reliability Specifications
7
1.2.6........................................Error Rates
8
1.2.7................Error Correction Code Specification
8
1.2.8..................................Defect Management
8
1.2.9..............................DC Power Requirements
9
1.2.10.........................Standards and Regulations
9
1.3.............................................Major Parts
10
1.3.1..............................Air Filtration System
10
1.3.2....................................Drive Mechanism
11
1.3.3.........................Head Positioning Mechanism
12
1.3.4.........................Read/Write Heads and Disks
13
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TABLE OF CONTENTS
2.0..........................................DISK DRIVE SETUP
15
2.1.................................................Jumpers
16
2.2.............................................Sector Size
16
2.3.......................................Service Connector
16
3.0...................................DISK DRIVE INSTALLATION
19
3.1................................................Mounting
19
3.2........................................Power-Up Testing
22
3.2.1.................................Self-Test Sequence
23
3.2.2............................Initialization Sequence
24
3.2.3.................................Self-Configuration
24
3.2.4...................................Buffering Scheme
24
3.3................................................Shipping
24
4.0........................................PHYSICAL INTERFACE
25
4.1....................................Host-Drive Interface
26
4.2.........................................Power Connector
28
4.3........................................Ground Connector
28
4.4.....................................Interface Connector
29
4.5.......................................Interface Signals
30
4.5.1................................Signal Descriptions
31
4.5.2.............................Signal Timing Diagrams
34
5.0..........................................AT-BUS REGISTERS
37
5.1....................................I/O Port Assignments
37
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TABLE OF CONTENTS
5.2...................................Register Descriptions
39
5.2.1......................................Data Register
39
5.2.2.....................................Error Register
40
5.2.3...........................Precompensation Register
41
5.2.4..............................Sector Count Register
41
5.2.5.............................Sector Number Register
41
5.2.6..............................Cylinder Low Register
41
5.2.7.............................Cylinder High Register
41
5.2.8................................Drive-Head Register
42
5.2.9....................................Status Register
42
5.2.10..................................Command Register
44
5.2.11.........................Alternate Status Register
44
5.2.12...........................Digital Output Register
44
5.2.13............................Drive Address Register
45
5.3..........................................Reset Response
46
6.0...........................................ATA COMMAND SET
47
6.1.........................................Error Reporting
48
6.2..........................................Translate Mode
50
6.3....................................Command Descriptions
50
6.3.1...................EXECUTE DRIVE DIAGNOSTIC Command
51
6.3.2...............................FORMAT TRACK Command
52
6.3.2.1......................Format Sectors as Good/Bad
53
6.3.2.2............................Reassign Bad Sectors
53
6.3.3.............................IDENTIFY DRIVE Command
54
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TABLE OF CONTENTS
6.3.4................INITIALIZE DRIVE PARAMETERS Command
56
6.3.5................................READ BUFFER Command
57
6.3.6..............................READ MULTIPLE Command
57
6.3.7.............................READ SECTOR(S) Command
58
6.3.8................................RECALIBRATE Command
58
6.3.9.......................................SEEK Command
59
6.3.10...........................SET BUFFER MODE Command
59
6.3.11.........................SET MULTIPLE MODE Command
59
6.3.12..........................VERIFY SECTOR(S) Command
60
6.3.13..............................WRITE BUFFER Command
60
6.3.14............................WRITE MULTIPLE Command
60
6.3.15...........................WRITE SECTOR(S) Command
61
APPENDIX A: CDB BIT DEFINITIONS...........................63
APPENDIX B: UNITS OF MEASURE..............................65
GLOSSARY...................................................67
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FIGURES
LXT-200A Product Specification & OEM Technical Manual
FIGURES
Figure 1ú1................................LXT-200A Disk Drive
1
Figure 1ú2..............................Air Filtration System
11
Figure 1ú3.........................Head Positioning Mechanism
12
Figure 2ú1.........................................PCB Layout
15
Figure 2ú2...........Connector Locations, Front View of Drive
17
Figure 3ú1..........Mechanical Outline, Bottom and Side Views
20
Figure 3ú2.................Mechanical Outline, Isometric View
21
Figure 3ú3................................Removable Faceplate
22
Figure 4ú1..........................Host-Drive Configurations
25
Figure 4ú2...............................Host-Drive Interface
27
Figure 4ú3................................Interface Connector
29
Figure 4ú4............Connector Locations, Rear View of Drive
30
Figure 4ú5....Interface 16 Bit Data Transfer to or from Drive
35
Figure 4ú6.......................................Reset Timing
35
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TABLES
LXT-200A Product Specification & OEM Technical Manual
TABLES
Table 1ú1..........................Performance Specifications
4
Table 1ú2...........................Functional Specifications
5
Table 1ú3................................Environmental Limits
6
Table 1ú4.................................Physical Dimensions
7
Table 1ú5..........................Reliability Specifications
7
Table 1ú6.........................................Error Rates
8
Table 1ú7...............................DC Power Requirements
9
Table 2ú1...............................Jumper Configurations
15
Table 2ú2...................Service Connector Pin Assignments
17
Table 3ú1.........................Initial Values of Registers
23
Table 4ú1.....................................Power Connector
28
Table 4ú2........................Power Connector Mating Parts
28
Table 4ú3....................Interface Connector Mating Parts
30
Table 4ú4...................................Interface Signals
32
Table 4ú5....................................Interface Timing
36
Table 5ú1................................I/O Port Assignments
38
Table 5ú2...................Selection Addresses and Functions
39
Table 5ú3..............................Error Bits in Register
40
Table 5ú4.................................Drive-Head Register
42
Table 5ú5................................Status Register Bits
42
Table 5ú6......................Alternate Status Register Bits
44
Table 5ú7...............................Digital Register Bits
44
Table 5ú8.........................Drive Address Register Bits
45
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TABLES
Table 5ú9.............................Initial Register Values
46
Table 6ú1.............Summary of Commands and Parameters Used
47
Table 6ú2...............................Valid Error Responses
49
Table 6ú3.........................................Error Codes
51
Table 6ú4............................Interleave Table Example
52
Table 6ú5....................................Flag Byte Values
52
Table 6ú6..............Format of Drive Parameters Information
55
Table 6ú7...............General Configuration Bit Definitions
56
Table 6ú8.........Initialize Drive Parameters Register Values
56
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1.0 DISK DRIVE DESCRIPTION
The LXT-200A disk drives are high capacity, high
performance, random access storage devices which use
nonremovable 3.5-inch disks as storage media. Each
disk surface employs one moveable head to access the
data tracks. See Figure 1ú1, LXT-200A Disk Drive. The
total formatted capacity of each drive is 201 megabytes
at 512 bytes per sector. The unformatted capacity is
234 megabytes.
The drive is designed to operate in an IBM PC/AT or
compatible computer. The host interface uses a task
file structure which is the standard interface for
PC/AT rigid disk controllers. Because the host
interfaces with the drive directly through the task
file register, an address decoder or buffer control
logic is required either in the mother board or in an
adapter board.
Figure 1ú1
LXT-200A Disk Drive
These disk drives include the Advanced Technology
Attachment (ATA) interface controller embedded in the
drive electronics. Some of the resulting benefits of
having an integrated controller include the elimination
of a separate controller printed circuit board (PCB),
reduction in the number of associated cables, and
elimination of the controller-specific power supply.
High performance is achieved through the use of a
rotary voice coil actuator and a closed loop servo
system using a dedicated servo surface. The innovative
MAXTORQª rotary voice coil actuator provides
performance usually achieved only with larger, higher
powered linear actuators. The closed loop servo system
and dedicated servo surface combine to allow state-of-
the-art recording densities (1,591 tracks per inch,
28,910 bits per inch) in a 3.5-inch package.
High capacity is achieved by a balanced combination of
high areal recording density, run-length limited (RLL)
data encoding techniques, and high density packaging
techniques. A three-zone implementation of 1,7 code is
used. Maxtor's advanced MAXPAKª electronic packaging
techniques use miniature surface-mounted devices to
allow all electronic circuitry to fit on one PCB.
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Advanced flexures and heads allow closer spacing of
disks, and therefore allow a higher number of disks in
a 3.5-inch package. Maxtor's integrated drive motor
and spindle design allows a deeper head disk assembly
(HDA) casting than conventional designs, thus
permitting four disks to be used.
The drive's size and mounting conform to the industry
standard 3.5-inch form factor for floppy and Winchester
disk drives, and the same direct current (DC) voltages
and connectors are used.
1.1 DRIVE FEATURES AND BENEFITS
Some key disk drive features include:
FEATURE BENEFITS
ú Storage capacity of 201 Maximum storage in the
megabytes, formatted at 3.5-inch disk drive
512 bytes per sector market; good upgrade from
(234 megabytes, the 5.25-inch disk drives
unformatted) which have less than 200
megabytes of capacity
ú Single PCB for servo, High reliability, ease of
read/write channel, and maintenance
controller functions
ú Thin film metallic media Higher bit density and
resolution, plus improved
durability
ú Brushless DC spindle Maximum storage capacity
motor inside hub
ú Industry standard DC No AC power required, ease
power supply re- of integration
quirements
ú Industry standard Ease of integration
physical size and
mounting
ú Low 10 watts power Less current requirements
dissipation of the power supply; low
power use
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Some key controller
features include:
ú AT task file register compatible command set
ú Extended command set support system auto-
configuration, self-diagnostic and media
certification
ú Sophisticated and efficient address translation,
allowing full usage of the zone bit encoding capacity
ú Address translation to maintain compatibility down
to the BIOS and register level
ú Programmable 56-bit error correction code (ECC)
ú Interleave of 1:1 supported
ú 32 kilobytes dual-ported buffer; two full tracks
capacity
ú High performance buffer manager that is capable of
disk and host transfers at the same time
ú Dedicated 16-bit microprocessor
ú Error map on disk
ú Standard 40 pin task file interface
ú Two drives may be daisy-chained on the interface and
configured as one Master and one Slave.
ú Sophisticated read-ahead caching utilizing the 32
kilobyte buffer to maximize data through put.
ú Multiple sector transfers are supported to reduce
system overhead on data transfers
The commands supported by the drive are listed and
discussed in chapter 6, ATA Command Set.
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1.2 PRODUCT SPECIFICATIONS
This section includes specifications for performance,
function, environmental limits, physical dimensions,
reliability, error rates, error correction code, and DC
power requirements. At the end of this section is a list
of the standards and regulations that apply to this family
of drives.
1.2.1 Performance Specifications
Table 1ú1
Performance Specifications
1.2.2 Functional Specifications
Table 1ú2
Functional Specifications
1.2.3 Environmental Specifications
Table 1ú3
Environmental Limits
1.2.4 Physical Specifications
Table 1ú4
Physical Dimensions
1.2.5 Reliability Specifications
Table 1ú5
Reliability Specifications
1.2.6 Error Rates
Table 1ú6
Error Rates
1.2.7 Error Correction Code Specification
The forward ECC polynomial is as follows:
X56+X52+X50+X43+X41+X34+X30+X26+X24+X8+1.
The reverse ECC polynomial is as follows:
X56+X48+X32+X30+X26+X22+X15+X13+X6+X4+1.
1.2.8 Defect Management
A complicated flaw scan process to generate the defect
list is done at the factory for every drive. As shipped
from the factory, the drive is pre-formatted with all
defects reassigned to spare sectors. When reassigning
defect sectors, the track is laid out again so that the
defect area is skipped. One-to-one interleave and skewing
factors are rearranged to maintain the streaming
performance. The drive is assumed to be error-free after
formatting.
1.2.9 DC Power Requirements
Table 1ú7
DC Power Requirements
1.2.10 Standards and Regulations
The Maxtor LXT-200A disk drives are intended to satisfy
the following standards and regulations:
UNDERWRITERS LABORATORIES (UL) is United States safety; UL
478, Standard for Safety, Electronic Processing Units and
Systems.
CANADIAN STANDARDS ASSOCIATION (CSA) is Canadian safety;
CSA C22.2 No. 220, 1986, Information Processing and
Business Equipment (Consumer and Commercial Products).
INTERNATIONAL ELECTROTECHNICAL COMMISSION (IEC) is
International safety commission; IEC 950 (formerly 380),
Safety of Information Technology Equipment.
FEDERAL COMMUNICATIONS COMMISSION (FCC) is United States
radiation emissions; Part 15, Subpart J, Class B Consumer
Computing Devices.
CAUTION: This equipment generates and uses radio
frequency energy, and may cause interference to radio and
television reception if not installed and used in strict
accordance with the instructions in this manual.
The drive has been tested and found to comply with the
limits for a Class B computing device, in accordance with
the specifications in Subpart J of Part 15 of FCC Rules,
which are designed to provide reasonable protection
against radio and television reception interference in a
residential installation. However, there is no guarantee
that interference will not occur in a particular
installation. If this equipment does cause interference
to radio or television reception, which can be determined
by turning the equipment off and on, the user is
encouraged to try to correct the interference using one or
more of the following measures:
ú reorient the receiving antenna
ú reorient the computer with respect to the receiver
ú move the computer away from the receiver
ú plug the computer into a different outlet, so that the
computer and receiver are on different branch circuits
If necessary, consult the dealer, or an experienced
radio/television technician, for additional suggestions.
You may find the FCC booklet How to Identify and Resolve
Radio TV Interference Problems helpful. This booklet is
available from the United States Government Printing
Office, Washington, D.C., 20402, stock number 004-000-
00345-4.
Maxtor is not responsible for any radio or television
interference caused by unauthorized modifications to the
drive. It is the responsibility of the user to correct
such interference.
1.3 MAJOR PARTS
The major elements of the drive are the air filter, the
head amplifier, the positioning motor, the read/write head
assembly, and the spindle motor. See Figure 1ú1, LXT-200A
Disk Drive. A brief discussion of some of these parts
appears below, in alphabetical order.
1.3.1 Air Filtration System
The disks and read/write heads are assembled in a Class
100 environment and then sealed within the head disk
assembly (HDA). The HDA contains an absolute filter,
mounted inside the casting, to provide constant internal
air filtration. See Figure 1ú2, Air Filtration System.
Figure 1ú2
Air Filtration System
1.3.2 Drive Mechanism
The HDA is a sealed subassembly containing the mechanical
portion of the drive. A brushless DC motor contained
within the spindle hub rotates the spindle and is con-
trolled by a dedicated microprocessor. The motor and
spindle are dynamically balanced to ensure a low vibration
level. Shock mounting is provided internally in the HDA
to minimize transmission of vibration through the frame.
The frame is the mechanical assembly holding the HDA and
printed circuit board (PCB).
1.3.3 Head Positioning Mechanism
The read/write heads are mounted on a head/arm assembly,
which is then mounted on a ball bearing supported shaft.
See Figure 1ú3, Head Positioning Mechanism. The voice
coil, an integral part of the head/arm assembly, lies
inside the magnet housing when installed in the drive.
Current from the power amplifier, controlled by the servo
system, induces a magnetic field in the voice coil which
either aids or opposes the field around the permanent
magnets. This reaction causes the voice coil to move
within the magnetic field. Since the head/arm assemblies
are connected to the voice coil, the voice coil movement
is transferred, through the pivot point, directly to the
heads, to position them over the desired cylinder.
Figure 1ú3
Head Positioning Mechanism
Actuator movement is controlled by the servo feedback
signal from the servo head. The servo information is
prewritten at the factory, and is used as a control signal
for the actuator to provide track crossing signals during
a seek operation, track following signals during on
cylinder operation, and timing information, such as index
and servo clock. The servo information also provides the
timing to divide a track into sectors used for data
storage. The servo control system has a dedicated
microprocessor for fast, optimized performance.
1.3.4 Read/Write Heads and Disks
The drive employs state-of-the-art sliders and flexures.
The configuration of the sliders and flexures provides
improved aerodynamic stability, superior head to disk
compliance, and a higher signal-to-noise ratio.
The media uses a nickel-cobalt metallic film that yields
high amplitude signals and very high resolution
performance compared to conventional oxide coated media.
It also provides an abrasion and impact resistant surface,
decreasing the potential for damage caused by shock and
vibration during shipping.
The data on each of the media surfaces is read by one
read/write head. There is one surface dedicated to servo
information in each drive.
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2.0 DISK DRIVE SETUP
Jumper locations are identified in Figure 2ú1, PCB Layout
and Table 2ú1, Jumper Configurations.
Figure 2ú1
PCB Layout
Table 2ú1
Jumper Configurations
2.1 JUMPERS
A ten pin header is provided that allows for installing or
removing jumpers to configure the drive.
The drive is shipped configured for use in a single drive
system.
Selection of the master drive is made by removing the
master/slave jumper. Selection of the slave drive is made
by installing the master/slave jumper.
Installing the drive active jumper provides a current
source for a drive active LED to pin 39 of the interface.
If the slave present jumper is installed, the drive active
jumper must not be installed.
Installing the slave present jumper provides an output on
DASP- that the slave drive is present. If the drive
active jumper is installed, the slave present jumper must
not be installed. The slave present jumper is not needed
if both drives in the system are the LXT-200A.
Installing the two drive system jumper on the master drive
indicates that a slave drive is present.
The manufacturing jumper is for internal use only.
Installing this jumper may result in damage to the drive
and loss of data.
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2.2 SECTOR SIZE
The drive is shipped from the factory formatted with 512-
byte sectors. The sector size is not changeable.
2.3 SERVICE CONNECTOR
Connector J4 in Figure 2ú2, Connector Locations, Front
View of Drive, is a service connector providing the RS-232
interface and the ability to carry the LED signal beyond
the drive. The RS-232 is used to load new firmware
updates to the drive. The service connector is a ten-pin
part. The mating connector is a Berg 6976410 part.
Figure 2ú2
Connector Locations, Front View of Drive
Pin assignments are as in Table 2ú2, Service Connector Pin
Assignments (also see Figure 4ú4, Connector Locations,
Rear View of Drive).
Table 2ú2
Service Connector Pin Assignments
When an LED is connected to pin nine (+) and pin ten (-),
that LED functions in the same manner as the LED which is
mounted on the drive's faceplate. This is typically used
in cases where the drive is mounted in a position where
the drive's LED is not visible and the faceplate is
removed.
Pins two through four are the RS-232 lines used to down
load firmware updates to the microprocessor which are then
stored on the disk. Pins three (transmit data) and four
(receive data) are the main communication lines. Pin two
is used to debug the processor and for a non-maskable
interrupt. Pins five and six are signal ground lines.
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3.0 DISK DRIVE INSTALLATION
This chapter includes the information you need to install
the drive, specifically mounting and shipping
considerations.
3.1 MOUNTING
The drive may be mounted in any orientation. In any final
mounting configuration, ensure that the operation of the
three shock mounts, which isolate the HDA from the frame,
are not restricted. Certain switching power supplies may
emanate electrical noise, which can degrade the specified
read error rate. For best results, orient the drive so
that the PCB assembly is not adjacent to these noise
sources.
Eight mounting holes, four on the bottom and two on each
side, are provided for mounting the drive into an
enclosure. The size and location of these holes, shown in
Figure 3ú1, Mechanical Outline, Bottom and Side Views, are
identical to industry standards. Overall height, width,
and depth, along with other key dimensions, are shown in
Figure 3ú1, and Figure 3ú2, Mechanical Outline, Isometric.
Figure 3ú1
Mechanical Outline, Bottom and Side Views
Figure 3ú2
Mechanical Outline, Isometric View
The faceplate is clipped to the front of the HDA and may
be removed in installations that do not require it. Lift
up on the faceplate clips and unplug the LED cable from
the PCB, as shown in Figure 3ú3, Removable Faceplate.
Figure 3ú3
Removable Faceplate
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3.2 POWER-UP TESTING
This section describes the sequence of events during drive
self-test and initialization sequences. The self-test
sequence is performed upon power up, and is followed by
the initialization sequence.
NOTE: The self-test sequence can also be initiated via the
EXECUTE DRIVE DIAGNOSTIC command which includes options
for more comprehensive diagnostics.
When the drive is reset, either by the host reset
interface pin, -RESET, or by the SRST bit the drive sets
the busy (BSY) bit immediately. Once the -RESET has been
removed and the drive has been reenabled, with the BSY bit
still set, the drive performs any necessary hardware
initialization, clears any previously programmed drive
parameters and reverts to the default condition, loads the
command block registers with their initial values, and
then clears the BSY bit. No interrupt is generated when
initialization is complete, and no self test is performed.
The initial values (hex) for the command block registers
are shown in Table 3ú1.
Table 3ú1
Initial Values of Registers
3.2.1 Self-Test Sequence
The self-test sequence is executed upon drive power up.
The self-test sequence verifies the integrity of the
hardware. This test is not an exhaustive hardware
diagnostic, but simply checks the major components for
full function. After the self-test is complete and the
circuitry is initialized (approximately 3 seconds), the
drive loads the task file registers with the results of
the self-test sequence, and clears the BSY bit.
The self-test sequence consists of the following events:
ú Hardware Reset Test - This routine tests the
microprocessor, buffer controller, and disk formatter.
If any of these tests fail, the disk drive can only be
reset by a power up.
ú Microprocessor Test - This routine tests the
microprocessor's internal memory, timers, and register
bank switching for proper operation.
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ú Buffer Controller Test - This routine tests the buffer
controller for proper operation. All the registers are
tested and the chip is engaged to access random-access
memory (RAM).
ú Disk Formatter Test - This routine tests the disk
formatter chip by writing and reading all possible
patterns to each of the disk formatter chip registers.
After the registers are tested, the interrupts are
tested to ensure that the formatter chip generates an
interrupt when a command completes.
If any portion of the self-test fails, except the hardware
reset test, the drive can be reset by a power up reset.
The failure of the hardware reset test is considered a
catastrophic failure and the controller can only be reset
from such a failure by a power up reset. If the drive
fails, the result is set in the task file register.
3.2.2 Initialization Sequence
The initialization sequence is executed for any one of the
following three reasons:
ú A power up sequence occurs.
ú The -RESET signal is asserted.
ú The BSY bit is set until the self-test is done and then
it is cleared.
3.2.3 Self-Configuration
When the drive powers up or is reset, it configures itself
in accordance with its default general drive parameters.
See Table 6ú6.
3.2.4 Buffering Scheme
The disk drive buffer is a 32-kilobyte FIFO buffer. There
are 32,767 bytes available for data storage. The buffer
controller allows transfer to the disk and from the host
simultaneously, or from the disk and to the host
simultaneously.
3.3 SHIPPING
At power down, the heads are automatically positioned over
the nondata, dedicated landing zone on each disk surface.
The automatic shipping lock solenoid is also engaged at
this time. Maxtor ships the drive in single and multipack
shipping containers. Users can ship the drive installed
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when the nonoperating shock and vibration limits are not
exceeded.
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4.0 PHYSICAL INTERFACE
This chapter describes the interface requirements of the
LXT-200A, which is compatible with the AT-BUS. Data is
transferred in a 16-bit wide parallel data path from the
host to the drive. Data transfer is controlled by
commands sent from the host. The drive performs all
operations necessary to write data on or read data from
the medium. Data read from the medium is placed in a
buffer prior to being transferred to the host.
This document describes the capabilities necessary to
operate the AT-Bus in a daisy chain configuration. This
allows two drives to be connected to the host. The
primary drive is designated as the master drive and the
secondary drive is designated as the slave drive. See
Figure 4ú1, Host-Drive Configurations.
Figure 4ú1
Host-Drive Configurations
4.1 HOST-DRIVE INTERFACE
The host-drive interface consists of single-ended TTL
compatible receivers and drivers connected with a 40-
conductor flat-ribbon cable. The maximum cable length is
twenty-four inches (0.61 meter) when using an asynchronous
protocol. Figure 4ú2, Host-Drive Interface, shows the pin
numbers and signal names of the host and the drive.
Figure 4ú2
Host-Drive Interface
4.2 POWER CONNECTOR
The drive receives power through a four-pin keyed
connector, drive connector terminal AMP P/N 61664-1 and
cable connector terminal AMP P/N 62137-2. The power
connector is shown in Table 4ú1. The recommended part
numbers for the mating connector are given in Table 4ú2.
Equivalent parts may be used.
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Table 4ú1
Power Connector
Table 4ú2
Power Connector Mating Parts
4.3 GROUND CONNECTOR
Logic ground and chassis ground are tied together and an
insert description lug is provided for connection to
system ground.
4.4 INTERFACE CONNECTOR
The interface connector is a 40-pin dual-row header
connector (see Figure 4ú3). The connector is oriented as
shown in Figure 4ú4. A key for the mating cable connector
is provided by the removal of pin 20. The corresponding
pin on the cable connector should be plugged. The cable
connector should be keyed to prevent the possibility of
installing it upside down.
Figure 4ú3
Interface Connector
Figure 4ú4
Connector Locations, Rear View of Drive
Recommended part numbers for the mating connector and
cables are shown in Table 4ú3. Equivalent parts may be
used.
Table 4ú3
Interface Connector Mating Parts
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4.5 INTERFACE SIGNALS
Signal names are shown in all upper case letters. Signals
can be asserted (active, true) in either a high (more
positive voltage) or low (less positive voltage) state. A
dash character (-) at the beginning or end of a signal
name indicates it is asserted at the low level (active
low). No dash or a plus character (+) at the beginning or
end of a signal name indicates it is asserted high (active
high). An asserted signal may be driven high or low by an
active circuit, or it may be allowed to be pulled to the
correct state by the bias circuitry. Control signals that
are asserted for one function when high and asserted for
another function when low are named with the asserted high
function name followed by a slash character (/), and the
asserted low function name followed with a dash (-). For
example, BITENA/BITCLR- enables a bit when high and clears
a bit when low. All signals are TTL compatible unless
otherwise noted. Negated means that the signal is driven
by an active circuit to the state opposite to the asserted
state (inactive, or false) or may be simply released (in
which case the bias circuitry pulls it inactive, or
false), at the option of the implementer.
4.5.1 Signal Descriptions
Table 4ú4 describes the drive interface signals and pins.
The signals are listed according to function, rather than
in numerical connector pin order. The table lists signal
name mnemonic, connector pin number, and whether the
signal is an input to or output from the drive. Following
the table is a description of each signal.
Table 4ú4
Interface Signals
Drive Reset: Reset signal from the host system which is
asserted during power and negated thereafter.
Drive Data Bus: A 16-bit bi-directional data bus between
the host and the drive. The lower 8 bits are used for
register and ECC byte access. All bits are used for data
word transfers. The drive data bus uses 24 mA tri-state
drivers.
Drive I/O Write: A write strobe, the rising edge of which
clocks data from the host data bus, DD0 through DD15, into
a register or the data port of the drive.
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Drive I/O Read: A read strobe, the falling edge of which
enables data from a register or the data port of the drive
onto the host data bus, DD0 through DD7 or DD0 through
DD15. The rising edge of DIOR- latches data at the host.
Drive Address Latch Enable: The drive address latch
enable signal is not used on the LXT-200A.
Drive Interrupt Request: An interrupt to the host system,
asserted only when the drive CPU has a pending interrupt,
the drive is selected, and the host asserts the IEN- bit
in the digital output register. When the IEN- bit is
negated, or the drive is not selected, this output is in a
high impedance state, regardless of the presence or
absence of a pending interrupt. The drive interrupt
request signal uses 24 mA tri-state drivers. The
interrupt is reset by a host read of the status register
or a host write to the command register.
I/O Control Select 16: An indicator to the host system
that the 16-bit data port has been addressed and that the
drive is prepared to send or receive a 16-bit data word.
The I/O control select uses 24 mA tri-state drivers.
Drive Address Bus: A three-bit binary coded address
supplied by the host when accessing a register or the data
port in the drive.
Passed Diagnostic: This signal is an input, for the
controller designated as a master, and is an output for
the controller designated as a slave. It is used to
indicate that a controller has successfully passed the
diagnostics. Upon the receipt of an EXECUTE DRIVE
DIAGNOSTICS command or the assertion of the -RESET signal,
the slave controller will set this line high. If the
command is completed without error, the slave will then
negate the PDIAG signal to indicate to the master
controller (which has this pin programmed as an input)
that the slave has passed diagnostics or completed the
reset. The master controller must wait a maximum of 5
seconds from the receipt the EXECUTE DRIVE DIAGNOSTIC
command or 3 msec after a reset to allow the slave's
report of status in the multi-controller mode (DASP-
asserted). In single controller applications, the master
will report status immediately after completion,
terminating the command.
Chip Select 1: The chip select signal is used to select
the command block registers.
Chip Select 3: The chip select signal is used to select
the control block registers.
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Drive Active or Slave Present: The use of this signal
depends on the setting of jumper W2. This signal
indicates either drive active or slave present. During a
power-up and drive initialization, this line is an output
from a slave drive, and an input to a master drive,
indicating a slave drive is present. If the drive is a
master, this line is an output which is asserted when the
drive is selected and being accessed (BSY is set), and may
be used to drive an activity LED. This is a 20 mA open
collector output.
Ground: Signal ground returns for the interface lines.
Key Pin: Pin used for keying the interface connector.
Reserved: These pins are currently defined as reserved
and are not connected in the drive.
4.5.2 Signal Timing Diagrams
Figure 4ú5, and 4ú6 show timing diagrams which define
relationships between the interface signals. Timing
standards are given for both 16 bit and 8 bit data
transfers in Table 4ú5. Note that these are minimum
acceptable interface timing requirements.
Figure 4ú5
Interface 16 Bit Data Transfer to or from Drive
Figure 4ú6
Reset Timing
Table 4ú5
Interface Timing
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5.0 AT-BUS REGISTERS
The LXT-200A drive is programmed by the host computer to
perform commands and return status to the host at command
completion. When two drives are daisy chained on the
interface, commands are written in parallel to both
drives, and for all except diagnostic commands, only the
selected drive executes the command. With diagnostic
commands, both drives execute the command and the slave
drive reports its status to the master drive via the
PDIAG- signal.
The drive selected is determined by the DRV bit in the
drive-head register (see section 5.2.8), and by a jumper
on the drive designating it as either a master or slave.
The LXT-200A also provides a jumper on the master drive
that indicates the presence of a slave drive. When the
DRV bit is cleared, the master drive is selected, and when
the DRV bit is set, the slave drive is selected. When
drives are daisy chained, one must be set as the master
and one as the slave. When a single drive is attached to
the interface it must be set as the master. Throughout
this document, drive selection always refers to the state
of the DRV bit, and the position of the master/slave
jumper.
5.1 I/O PORT ASSIGNMENTS
Input and output to or from the drive is through an I/O
port (see Table 5ú1) that routes the input or output data
to or from fourteen registers (selected) by a code on the
CS1FX-, CS3FX-, DA2, DA1, DA0, DIOR- and DIOW- lines from
the host. Ten of the registers are used for commands to
the drive or status, one is the data port and three are
used for control and alternate status. These are referred
to herein as the command block registers and the control
block registers. Table 5ú2 lists these registers and the
addresses that select them, together with the functions of
addresses that do not select one of the registers. Logic
conventions are 1 = signal asserted; 0 = signal negated; x
= does not matter which it is.
Table 5ú1
I/O Port Assignments
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Table 5ú2
Selection Addresses and Functions
5.2 REGISTER DESCRIPTIONS
The following paragraphs describe the operations of the
registers listed in Table 5ú2. The error,
precompensation, sector count, sector number, cylinder
low, cylinder high, drive-head, and command register are
accessible only when the BSY bit in the status register is
cleared.
5.2.1 Data Register
The data register is used to transfer the data during read
and write operations. It is also used to transfer the
sector table during the format commands. All data
transfers are 16 bits wide except for the transfer of ECC
bytes which are 8 bits wide. The transfer of ECC bytes
only occurs during read or write long operations. The
host can access the data register only when DRQ is set in
the status register.
5.2.2 Error Register
The error register contains status from the last command
executed by the drive. The contents of this register are
valid only when the error bit (ERR) is set in the status
register, unless the drive has just powered up or
completed execution of its internal diagnostic, in which
case the register contains a status code (see section
5.2.9). The error bits in the register are defined in
Table 5ú3.
Table 5ú3
Error Bits in Register
A bad block (BBK) bit of one indicates that a bad block
mark was detected in the requested sector's ID field.
An uncorrectable data (UNC) bit of one indicates that an
uncorrectable data error has been encountered.
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An ID not found (IDNF) bit of one indicates that the
requested sector's ID field could not be found.
An aborted command (ABRT) bit of one indicates that the
requested command has been aborted due to a drive status
error (not ready, write fault, etc.) or because the
command code is invalid.
A track 0 not found (TK0NF) bit of one indicates that
track 0 has not been found during a RECALIBRATE command.
An address mark not found (AMNF) bit of one indicates that
the data address mark has not been found after finding the
correct ID field.
Reserved indicates that this bit is set to zero.
Error bits set to zero indicate that no error was found.
5.2.3 Precompensation Register
The precompensation register is used to enable or disable
the Read Look-Ahead feature (see section 6.3.10).
5.2.4 Sector Count Register
The sector count register defines the number of sectors of
data to be read or written. If the value in this register
is zero, a count of 256 sectors is specified. This count
is decremented as each sector is read so the register
contains the number of sectors left to access in the event
of an error in a multisector operation. The contents of
this register define the number of sectors per track when
executing an INITIALIZE DRIVE PARAMETERS or FORMAT
command.
5.2.5 Sector Number Register
The sector number register contains the starting sector
number for any disk access. At the completion of each
sector, and at the end of the command, this register is
updated to reflect the last sector read correctly, or the
sector on which an error occurred.
5.2.6 Cylinder Low Register
The cylinder low register contains the low order eight
bits of the starting cylinder address for any disk access.
At the completion of each sector, and at the end of the
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command, this register is updated to reflect the current
cylinder number.
5.2.7 Cylinder High Register
The cylinder high register contains the high order bits of
the starting cylinder address for any disk access. At the
completion of each sector, and at the end of the command,
this register is updated to reflect the current cylinder
number. The most significant bits of the cylinder address
should be loaded into the cylinder high register.
5.2.8 Drive-Head Register
This register specifies the drive and head numbers. At
the completion of each sector, and at the end of the
command, this register is updated to reflect the currently
selected head. See Table 5ú4, Drive-Head Register.
Table 5ú4
Drive-Head Register
It is recommended that the sector size bits be set to 01b
to indicate the 512 byte sector size. However, these bits
are ignored by the LXT-200A.
The drive (DRV) bit is the binary encoded drive selected
number. When this bit is cleared, the master drive is
selected, and when this bit is set, the slave drive is
selected.
The head number field is the four bit binary encoded head
select number.
5.2.9 Status Register
The status register contains the drive status. The
contents of this register are updated at the completion of
each command. If the busy bit is asserted, no other bits
are valid. The host reading this register when an
interrupt is pending is considered to be the interrupt
acknowledge, and any pending interrupt is therefore
cleared whenever this register is read. The bits in this
register are defined below in Table 5ú5.
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Table 5ú5
Status Register Bits
The busy (BSY) bit set whenever the drive has access to
the command block registers, and the host is prevented
from accessing the command block. This bit is set under
the following circumstances:
ú At assertion of the RESET- signal on the
interface, or at setting of the SRST bit in the
digital output register.
ú Immediately upon host write of the command
register with a READ, READ LONG, READ BUFFER SEEK,
RECAL, INITIALIZE DRIVE PARAMETERS, VERIFY,
IDENTIFY, or DIAGNOSTIC command.
ú Immediately following transfer of 512 bytes of
data during execution of a WRITE, FORMAT TRACK, or
WRITE BUFFER command, or 512 bytes of data and the
appropriate number of ECC bytes during the execution
of a WRITE LONG command.
When the BSY bit is set, any host read of a shared
register is inhibited and the status register is read
instead.
When there is an error, the drive ready indication (DRDY)
bit is not changed until the status register is read by
the host, at which time the bit again indicates the
current readiness of the drive. This bit should be
cleared at power up and remain cleared until the drive is
up to speed and ready to accept a command.
When there is an error, the drive write fault (DWF) bit is
not changed until the status register is read by the host,
at which time the bit again indicates the current fault
status.
The drive seek complete (DSC) bit is always set after the
drive is ready.
When set, the data request (DRQ) bit indicates that the
drive is ready for transfer of a word or byte of data
between the host and the data port.
The corrected data (CORR) bit, which is set when a
correctable data error has been encountered and the data
has been corrected. This condition does not terminate a
multisector read operation.
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The index (IDX) bit is set once per disk revolution.
When set, the error (ERR) bit indicates that the previous
command ended in error. The other bits in the status
register, and the error register have additional
information as to the cause of the error.
5.2.10 Command Register
The eight bit code written to this register transfers to
the drive the command that the host is requesting.
Command execution begins immediately after this register
is written. See chapter 6 for detailed information on the
ATA command set.
5.2.11 Alternate Status Register
The alternate status register contains the same
information as the status register in the command block.
The only difference is that reading this register does not
imply interrupt acknowledge or clear a pending interrupt.
See Table 5ú6, Alternate Status Register Bits.
Table 5ú6
Alternate Status Register Bits
See section 5.2.9 for definitions of the bits in this
register.
5.2.12 Digital Output Register
The digital output register contains two control bits.
See Table 5ú7, Digital Register Bits.
Table 5ú7
Digital Register Bits
The drive is held reset when the host software reset
(SRST) bit is set, and enabled when this bit is cleared.
If two drives are daisy chained on the interface, this bit
resets and enables both drives simultaneously.
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The not interrupt enabled (NIEN) bit is the enable bit for
the drive interrupt to the host. When this bit is set,
and the drive is selected, the host interrupt, INTRQ, is
enabled, through a tri-state buffer, to the host. When
this bit is cleared, or the drive is not selected the
INTRQ pin is in a high impedance state, regardless of the
presence or absence of a pending interrupt.
Bits in Table 5ú7 marked N/A are not used
5.2.13 Drive Address Register
The drive address register loops back the drive select and
head select addresses of the currently selected drive.
The bits in this port are as described below in Table 5ú8.
Table 5ú8
Drive Address Register Bits
Bits marked N/A are undriven by the drive. When the host
reads the drive address register, this bit is in a high
impedance state. This is to prevent conflict with the
floppy disk interface.
The not write gate (NWTG) bit is cleared when writing to
the drive is in progress.
The head selected field is the one's complement of the
binary coded address of the head number field. See table
5ú4, Drive-Head Register.
The not drive select bit for drive 1 (NDS1) is cleared
when drive 1 is selected and active. The not drive select
bit for drive 0 (NDS0) is cleared when drive 0 is selected
and active.
NOTE: Use care interpreting these bits, as they do not
always represent the expected status of drive operations
at the instant the status was put into this register.
This is because of the use of caching, translate mode and
master/slave drives each having its own embedded
controller.
5.3 RESET RESPONSE
When the drive is reset, either by the host reset
interface pin, RESET-, or by the SRST bit the drive sets
BSY immediately. Once the reset has been removed and the
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drive has been re-enabled, with BSY still set, the drive
performs any necessary hardware initialization, clears any
previously programmed drive parameters and reverts to the
default condition, loads the command block registers with
their initial values, and then clears BSY. No interrupt is
generated when initialization is complete, and no self-
test is performed. The initial values (hex) for the
command block registers are shown in Table 5ú9.
Table 5ú9
Initial Register Values
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6.0 ATA COMMAND SET
Commands are issued to the drive by loading the pertinent
registers in the command block with the needed parameters,
setting the not interrupt enable bit, NIEN in the digital
output register, and then writing the command code to the
command register. Execution begins as soon as the command
register is written. A summary of commands and the re-
quired parameters is given in Table 6ú1.
Table 6ú1
Summary of Commands and Parameters Used
If the long bit (L) is set to one, READ/WRITE LONG
commands are executed. If the long bit is zero, normal
READ/WRITE commands are performed.
A retry (R) bit of zero enables retries. A retry bit of
one disables retries. Retries are automatically re-
enabled at the end of the command.
PC is the write precompensation register.
SC is the sector count register.
SN is the sector number register.
CY is the cylinder register.
DH is the drive-head register
Y means the register contains a valid parameter for this
command. For the drive-head register, Y means that both
the drive and head parameters are used.
N means the register does not contain a valid parameter
for this command.
D means only the drive parameter is valid and not the head
parameter.
X means the value is not relevant.
6.1 ERROR REPORTING
The errors that are valid for each command are defined in
the matrix shown in Table 6ú2.
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Table 6ú2
Valid Error Responses
BBK is bad block detected.
UNC is uncorrectable data error.
IDNF is requested ID not found.
ABRT is aborted command error
TK0NF is track 0 not found error.
AMNF is data address mark not found error.
DRDY is disk drive not ready detected.
DWF is disk drive write fault detected.
DSC is disk drive seek complete not detected.
CORR is corrected data error.
ERR is the error bit in the status register.
6.2 TRANSLATE MODE
The drive always operates in the translate mode because it
uses zoned recording techniques. The drive firmware
translates requests from the host into corresponding
physical sector requests.
Because the host communicates with the drive using
physical drive parameters (i.e., cylinder number, head
number, and sector number), a mapping address translation
is needed to fully utilize the capacity of the drive.
This also makes selecting a drive type from the BIOS
tables easier. The drive type selected should have a
capacity equal to or less than 201 megabytes.
6.3 COMMAND DESCRIPTIONS
The drive implements the following standard commands:
EXECUTE DRIVE DIAGNOSTIC
FORMAT TRACK
INITIALIZE PARAMETERS
READ SECTOR(S)
RECALIBRATE
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SEEK
VERIFY SECTOR(S)
WRITE SECTOR(S)
The drive implements the following extended commands:
IDENTIFY DRIVE
READ BUFFER
READ MULTIPLE
SET BUFFER MODE
SET MULTIPLE
WRITE BUFFER
WRITE MULTIPLE
6.3.1 EXECUTE DRIVE DIAGNOSTIC Command
The EXECUTE DRIVE DIAGNOSTIC command performs the internal
diagnostic tests implemented by the drive. The diagnostic
tests are executed only upon receipt of this command.
They are not to be executed automatically at power up or
after a reset. The drive sets BSY immediately upon
receipt of the command. If the drive is a slave, the disk
active/slave present signal is always asserted.
The drive then performs the diagnostic tests and reports
the results. If the drive is a master and a slave is
connected, it waits up to 5 seconds for the slave to
complete diagnostics, checks the state of the PDIAG signal
and then reports the diagnostic results. If the drive is
a master and a slave is not connected, it reports only its
diagnostic results. Following this, the drive clears BSY,
and generates an interrupt.
The value in the error register should be viewed as an
eight-bit code value and not as bit significant flags as
described in section 5.2.2. Table 6ú3 defines the eight-
bit code values and their meanings.
Table 6ú3
Error Codes
NOTE: If the slave drive fails diagnostics, the master
drive "ORs" gates 80 hex with its own status and loads
that code into the error register. If the slave drive
passes diagnostics or there is no slave drive connected,
the master drive "ORs" 00 with its own status and loads
that code into the error register.
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6.3.2 FORMAT TRACK Command
The FORMAT TRACK command initializes the data fields to
00h for the virtual track. Because the drive uses a zoned
bit recording technique, the physical track and the
virtual track are not always the same. The drive is
always operating in translation mode.
As soon as the command register is written, the drive sets
the DRQ bit in the status register and waits for the host
to fill the buffer with 512 bytes of interleave table.
Once all the data is transferred, the drive sets BSY and
starts the command execution. At the completion of
execution, the drive resets BSY and generates an
interrupt.
The interleave table is made up of two bytes per sector
for the track. The host should fill the remaining bytes
with 00. The first byte is the sector flag byte (fb).
The second byte is the logical sector number (sn). See
Table 6ú4, Interleave Table Example.
Table 6ú4
Interleave Table Example
The logical sector ranges from 1 to the maximum sector
number specified in the sector count register. If a
logical sector number is out of this range, or if any
duplication occurs, the FORMAT TRACK command is aborted.
The flag byte values are shown in Table 6ú5.
Table 6ú5
Flag Byte Values
An invalid flag causes the command to be aborted.
In order to keep the drive sector reassignment scheme
intact, the drive rejects commands when the interleave
table has both 80h and 40h flags. That is, the FORMAT
TRACK command cannot have mark bad and reassign sectors in
the same track.
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6.3.2.1 FORMAT SECTORS AS GOOD/BAD
If the interleave consists of 00h and 80h or only 00h in
the flag bytes, the controller reformats the ID field of
every sector in that logical track, marks the sector ID
either good or bad according to the interleave table.
When the controller encounters a bad sector mark in the
sector ID while reading or writing sectors, a bad sector
flag detected error code (80h) will be posted and the
command terminated. This will halt the streaming perfor-
mance of the drive.
Due to the cylinder/head skew, and the defect reassignment
scheme employed in the drive, the logical sector is not
mapped into a predictable physical sector location. The
controller has to read the IDs for the whole track in
order to figure out the physical offset to the index
pulse. When formatting, the controller counts the sector
pulse after the index to get to the right sector position
and start the format operation.
The data field of the logical sector is written with data
pattern 00 after the format is done.
The drive issues an interrupt to the host at the
completion of this command.
6.3.2.2 REASSIGN BAD SECTORS
If the interleave table consists of 00h and 40h, the
controller executes a reassign block operation. For
reassigning sectors, the controller uses the spare sector
in the same physical track to relocate the sector. If a
spare sector is not available, alternate sectors in the
reserved alternate cylinder are used.
Before reassigning the block, the data in the whole
physical track is backed up in an alternate cylinder.
After reassigning, the data is restored to the track.
While backing up the track, any sector, other than the
reassigned block or a known defect in the Plist or Glist,
found to be bad will terminate the command with a SECTOR
NOT FOUND error (error code 10h). The sector address is
posted in the task file register. The host should re-is-
sue the FORMAT TRACK command that includes the new bad
sector in the interleave table.
After backing up the data of the track, the track is
reformatted with pre-defined interleave and headskew. The
reassigned sector location is skipped, the following
sectors are pushed to the next sector location. If no
spare sector is available on the track, the remaining
sectors are pushed to the spare cylinder area.
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After the sector is reassigned, the defect sector
locations are added to the drive Glist. After reassigning
the block, the data in the reassigned block may be
altered, but the data in all other blocks is preserved.
The drive issues an interrupt to the host at the
completion of this command.
6.3.3 IDENTIFY DRIVE Command
The IDENTIFY DRIVE command enables the host to receive
parameter information from the drive. When the command is
issued, the drive sets BSY, stores the required parameter
information in the sector buffer, sets the DRQ bit, and
generates an interrupt. The host then reads the
information out of the sector buffer. The parameter words
in the buffer have the arrangement and meaning as shown in
Table 6ú6, Format of Drive Parameters Information. All
reserved bits or words should be zeroes.
The data is transferred low byte first then high byte.
Table 6ú6
Format of Drive Parameters Information
The bits in the general configuration word are defined in
Table 6ú7.
Table 6ú7
General Configuration Bit Definitions
6.3.4 INITIALIZE DRIVE PARAMETERS Command
The INITIALIZE DRIVE PARAMETERS command enables the host
to control certain drive parameters. The drive uses 15
heads, 32 sectors, and 816 cylinders as its virtual
configuration, but will accept any valid combination of
parameters. If the configuration requested exceeds the
capacity of the drive, an ABORTED COMMAND error is
returned. Table 6ú8 enumerates the range of register
values for this function.
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Table 6ú8
INITIALIZE DRIVE PARAMETERS Register Values
The Drive-Head value is checked. The Sector Count value
is checked and if the value is not in the range of 1 to
63, an aborted command error is returned. The Cylinder
value is not checked.
6.3.5 READ BUFFER Command
The READ BUFFER command allows the host to read the
current contents of the buffer. The number of sectors to
be transferred is specified in the sector count register.
If the number of sectors to be transferred exceeds the
buffer size then an aborted command error is returned. A
value of zero in the sector count register requests 256
sectors to be transferred; in which case one 512 byte
transfer is allowed and an ABORTED COMMAND error is
returned. When the command register is written, the drive
sets the BSY bit, prepares the buffer, sets DRQ bit,
clears the BSY bit, and generates an interrupt. The host
then reads the data from the buffer. An interrupt is
generated for each sector.
6.3.6 READ MULTIPLE Command
The READ MULTIPLE command performs similarly to the READ
SECTOR(S) command except that data transfers are in
multiple sector blocks and the long bit is not valid.
Command execution is identical to the READ SECTOR(S)
operation but with several sectors transferred to the host
as a block without intervening interrupts and requiring
only DRQ qualification of the transfer at the start of the
block, not on each sector. The block count, which is the
number of sectors to be transferred as a block, is
programmed by the SET MULTIPLE MODE command, which must be
executed prior to the READ MULTIPLE command. When the
read multiple command is issued, the sector count register
contains the number of sectors (not the number of blocks
or the block count) requested. If this sector count is
not evenly divisible by the block count, as many full
blocks as possible are transferred, followed by a final,
partial block transfer. The partial block transfer will
be for N sectors, where N = (sector count) modulo (block
count).
If the READ MULTIPLE command is attempted before the SET
MULTIPLE MODE command has been executed or when READ
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MULTIPLE commands are disabled, the READ MULTIPLE
operation will be rejected with an ABORTED COMMAND error.
Disk errors encountered during READ MULTIPLE commands are
reported at the beginning of the block or partial block
transfer, but DRQ is still set and the transfer will take
place as it normally would, including transfer of
corrupted data, if any. Subsequent blocks or partial
blocks are transferred only if the error was a correctable
data error. All other errors cause the command to stop
after transfer of the block which contained the error.
Interrupts are generated when DRQ is set at the beginning
of each block or partial block.
6.3.7 READ SECTOR(S) Command
The READ SECTOR(S) command reads from 1 to 256 sectors as
specified in the command block (sector count equal to 0
requests 256 sectors), beginning at the specified sector.
As soon as the command register is written, the drive sets
the BSY bit and begins execution of the command. If the
drive is not already on the desired track, a SEEK is per-
formed to the desired track. The drive then searches for
the appropriate ID field.
If retries are disabled and two index pulses have occurred
without error free reading of the requested ID, an ID NOT
FOUND error is posted in the error register. If retries
are enabled, up to a vendor specific number of attempts
may be made to read the requested ID before reporting an
error. If the ID is read correctly, the data address mark
must be recognized within a specified number of bytes, or
the data address mark not found error is reported. Once
the data address mark is found, the data field is read
into the sector buffer. Error bits are asserted if an
error was encountered. The DRQ bit is set, and an in-
terrupt is generated. The DRQ bit is always set,
regardless of the presence or absence of an error
condition at the end of the sector. Upon command
completion, the command block registers contain the
cylinder, head, and sector numbers of the last sector
read.
Multiple sector reads set DRQ and generate an interrupt
when the sector buffer is filled at the completion of each
sector. The drive is then ready for the data to be read
by the host. DRQ is cleared and BSY is set immediately
when the host empties the sector buffer. If an error
occurs during a multiple sector read, the read terminates
at the sector where the error occurred. The command block
registers contain the cylinder, head, and sector numbers
of the sector where the error occurred. The host may then
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read the command block to determine what error has
occurred, and on which sector. If the error was either a
correctable data error or an uncorrectable data error, the
flawed data is loaded into the sector buffer.
A READ LONG command is executed by setting the long bit in
the command code. The READ LONG command returns the data
(512 bytes, 16 bit wide) and the ECC bytes (7 bytes, 8
bits wide) contained in the data field of the desired
sector. During a READ LONG command, the drive does not
check the ECC bytes to determine if there has been any
type of data error. Only single sector READ LONG
operations are supported.
6.3.8 RECALIBRATE Command
The RECALIBRATE command moves the read-write heads from
anywhere on the disk to cylinder zero. Upon receipt of
the command, the drive sets BSY and issues a SEEK command
to cylinder zero. The drive then waits for the SEEK to
complete before updating status, clearing BSY and
generating an interrupt. If the drive cannot reach
cylinder zero, the error bit is set in the status
register, and the track zero bit set in the error
register.
6.3.9 SEEK Command
The SEEK command initiates a seek to the track and selects
the head specified in the command block. The drive need
not be formatted for a SEEK to execute properly. When the
command is issued, the drive sets BSY in the status
register, initiates the SEEK, clears BSY, and generates an
interrupt. The SEEK is not completed before the drive
returns the interrupt. The drive SEEK complete bit is not
toggled. If a new command is issued to a drive while a
SEEK is being executed, the drive delays with BSY set for
the SEEK to complete before executing the new command. If
the cylinder is not valid, the SEEK is not performed. The
SEEK complete bit is set, and a command abort error is
reported.
6.3.10 SET BUFFER MODE Command
The SET BUFFER MODE command enables or disables the Read
look-ahead feature. Prior to command issuance, the write
precompensation register should be loaded with either AAh
to enable, or 55h to disable read look-ahead operation.
Upon receipt of the command, the controller asserts and
checks at the write precompensation register contents. If
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the register contents are either 55h or AAh, the
appropriate mode is selected. Any other value in the
register results in an aborted command. At command
completion, the controller clears BSY and generates an
interrupt. At power up, or after a software or hardware
reset, the default mode is read look-ahead enabled.
6.3.11 SET MULTIPLE MODE Command
The SET MULTIPLE MODE command enables the drive to perform
READ and WRITE MULTIPLE operations and establishes the
block count for these commands. Prior to command issuance,
the sector count register should be loaded with the number
of sectors per block. The drive supports block sizes of
1, 2, 4, 8, 16, and 32 sectors, to maintain 1:1
performance. Upon receipt of the command, the controller
sets BSY and checks the sector count register contents.
If the register contents are a valid and the block count
is supported, the value is loaded for all subsequent READ
and WRITE MULTIPLE commands and execution of those
commands is enabled. Any unsupported block count in the
register results in an ABORTED COMMAND error and READ and
WRITE MULTIPLE commands being disabled. If the sector
count register contains 0 when the command is issued, READ
and WRITE MULTIPLE commands are disabled. Once the
appropriate action has been taken, the controller clears
BSY and generates an interrupt. At power up, or after a
hardware or software reset, the default mode is read and
write multiple disabled.
6.3.12 VERIFY SECTOR(S) Command
The VERIFY SECTOR(S) command is identical to the READ
SECTOR(S) command, except that DRQ is never set. No data
is transferred to the host and the long bit is not valid.
The drive sets BSY as soon as the command register is
written and then clears BSY and generates an interrupt
when the requested sectors have been verified. Upon
command completion, the command block registers contain
the cylinder, head, and sector number of the last sector
verified.
If an error occurs during a multiple sector verify, the
read terminates at the sector where the error occurs. The
command block registers contain the cylinder, head, and
sector number of the sector where the error occurred.
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6.3.13 WRITE BUFFER Command
The WRITE BUFFER command enables the host to write to the
buffer. The number of sectors to be transferred is
specified in the sector count register. If the number of
sectors to be transferred exceeds the buffer size, an
ABORTED COMMAND error is returned. A value of zero in the
sector count register requests 256 sectors to be
transferred; in which case one 512 byte transfer is
allowed and an ABORTED COMMAND error is returned. When
this command register is written, the drive sets the BSY
bit, prepares the buffer, sets the DRQ bit, clears the BSY
bit, and generates an interrupt. The host then writes the
data to the buffer. An interrupt is generated for each
sector.
6.3.14 WRITE MULTIPLE Command
The WRITE MULTIPLE command performs similarly to the WRITE
SECTOR(S) command except that the controller sets BSY
immediately upon receipt of the command. Data transfers
are multiple sector blocks, and the long bit is not valid.
Command execution is identical to the write sector(s)
operation, but with several sectors transferred by the
host as a block without intervening interrupts and only
requiring DRQ qualification of the transfer at the start
of the block, not on each sector. The block count, which
is the number of sectors to be transferred, is programmed
by the SET MULTIPLE MODE command, which must be executed
prior to the WRITE MULTIPLE command. When the WRITE
MULTIPLE command is issued, the sector count register
contains the number of sectors (not the number of blocks
or the block count) requested. If this sector count is
not evenly divisible by the block count, as many full
blocks as possible are transferred, followed by a final,
partial block transfer. The partial block transfer is for
N sectors, where N = (sector count) modulo (block count).
If the WRITE MULTIPLE command is attempted before the SET
MULTIPLE MODE command has been executed or when WRITE
MULTIPLE commands are disabled, the WRITE MULTIPLE
operation is rejected with an ABORTED COMMAND error.
All disk errors encountered during WRITE MULTIPLE commands
are reported after the attempted disk write of the block
or partial block transferred. The write operation ends
with the sector in error, even if it was in the middle of
a block. Subsequent blocks are not transferred in the
event of an error. Interrupts are generated when DRQ is
set at the beginning of each block or partial block.
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6.3.15 WRITE SECTOR(S) Command
The WRITE SECTOR(S) command writes from 1 to 256 sectors
as specified in the command block (sector count equal to 0
requests 256 sectors), beginning at the specified sector.
As soon as the command register is written, the drive sets
the DRQ bit and waits for the host to fill the buffer with
the data to be written. An interrupt is not generated to
start the first 512 byte data transfer operation; however,
an interrupt is generated for each successive 512 byte
transfer until the buffer is full, the sector count is
exhausted, or an error occurs.
If the drive is not already on the desired track, a SEEK
is performed to the desired track. The drive then
searches for the appropriate ID field. If retries are
disabled and two index pulses have occurred without an
error free reading of the requested ID, an ID NOT FOUND
error is posted in the error register. If retries are
enabled, a specific number of attempts are made to read
the requested ID before reporting an error. If the ID is
read correctly, the data loaded in the buffer is written
to the data field of the sector, followed by the ECC
bytes. Upon command completion, the command block
registers contain the cylinder, head, and sector number of
the last sector written.
Multiple sector writes set DRQ and generate an interrupt
each time the buffer is ready to be filled. DRQ is cleared
and BSY is set immediately when the host fills the sector
buffer. If an error occurs during a multiple sector write,
writing terminates at the sector where the error occurs.
The command block registers contain the cylinder, head,
and sector number of the sector where the error occurred.
The host may then read the command block to determine
which error has occurred, and on which sector.
A WRITE LONG is executed by setting the long bit in the
command code. The WRITE LONG command writes the data (512
bytes, 16 bit wide) and the ECC bytes (7 bytes, 8 bits
wide) directly from the sector buffer. The drive does not
generate the ECC bytes itself. Only single sector WRITE
LONG operations are supported.
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APPENDIX A: CDB BIT DEFINITIONS
Abbreviation Meaning
ABRT aborted command bit
AMNF address mark not found bit
BBK bad block bit
BSY busy bit
CORR corrected data bit
DRDY drive ready indication bit
DRQ data request bit
DRV master or slave drive select bit
DSC drive seek complete bit
DWF drive write fault bit
ERR error bit
IDNF ID not found bit
IDX index bit
L long bit
NDS0 not drive select bit for 0
NDS1 not drive select bit for 1
NIEN not interrupt enable bit
NWTG not write gate bit
R retry bit
SRST host software reset bit
TK0NF track 0 not found bit
UNC uncorrectable data bit
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APPENDIX B: UNITS OF MEASURE
Abbreviation Meaning
A/m amps per meter
AWG American wire gauge
bpi bits per inch
dBa decibel, A-weighted
fci flux changes per inch
g gram
Gbyte gigabyte
Hz hertz
mA milliamp
æA microamp
Mbit megabit
Mbyte megabyte
æm micrometer
msec millisecond
æsec microsecond
nsec nanosecond
Oe oersted
RH relative humidity
rpm revolutions per minute
tpi tracks per inch
xxb binary values
xxh hexadecimal values
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GLOSSARY
assert. A signal driven to the true state.
async. Asynchronous
bit. Binary digit
byte. Eight consecutive binary digits
clear. A bit has a value of zero.
connect. The function that occurs when an initiator
selects a target to start an operation.
CRC. Cyclic redundancy check
CSA. Canadian Standards Association
DC. Direct current
DMA. Direct memory access
ECC. Error correction code
EIA. Electrical Industry Association
EPROM. Erasable programmable read only memory
FCC. Federal Communication Commission
FIFO. First-in, first-out storage and retrieval technique
firmware. Computer programs encoded permanently into a
ROM
G. Constant of gravitation
gnd. Ground
hard error. An error due to faulty equipment,
transmission techniques, recording media, etc.
HDA. Head disk assembly
hex. Hexadecimal
I/O. Input and/or output
ISG. Inter-sector gap
ISO. International Standardization Organization
LBA. Logical block address
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LED. Light-emitting diode
logical thread. The logical path which exists between an
initiator's memory and a bus device LUN, even though
the physical path may be disconnected.
logical unit. A physical or virtual device addressable
through a target.
LSB. Least significant byte
LSTTL. Low power, Schotky transistor-transistor logic
LUN. Logical unit number, an encoded 3-bit identifier for
the logical unit.
æC. Microcomputer
æcomputer. Microcomputer
MFM. Modified frequency modulation (encoding)
MTBF. Mean time between failures
MTTR. Mean time to repair
N.C. No connection
negate. A signal driven to the false state
nom. Nominal
OEM. Original equipment manufacturer
one. True signal value
parity. A method of checking the accuracy of binary
numbers
PCB. Printed circuit board
PLL. Phase-locked loop
PLO. Phase-locked oscillator
P/N. Part number
POH. Power On hours
P-P. Peak to peak
PROM. Programmable read only memory
RAM. Random-access memory
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reconnect. The function that occurs when a target selects
an initiator to continue an operation after disconnect.
release. The act of allowing the cable terminators to
bias the signal to the false state (by placing the
driver in the high impedance condition).
req. Request
reserved. Bits, bytes, fields and code values that are
set aside for future standardization.
RLL. Run-length limited
ROM. Read-only memory
R/W. Read and/or write
set. A bit has a value of one.
TLA. Top level assembly
TTL. Transistor-transistor logic
typ. Typical
UL. Underwriter's Laboratories, Inc.
UNC. Unified National Coarse
UNF. Unified National Fine
VDE. Verband Deutscher Electrotechniker
zero. False signal code
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