How to Set the PCI-0640x for ATA PIO w/Flow Control Timing Modes
---------------------------------------------------------------

From the Small Form Factor Committee's latest proposals and ATA-2 (as of
January 1994), the minimum times in ns for PIO w/flow control modes are:

        t1      t2      t2i     t0
        addr    active  recover cycle
        setup   pulse   pulse   time
        (min)   (min)   (min)   (min)

Mode 0  70      165     *       600
Mode 1  50      125     *       383
Mode 2  30      100     *       240
Mode 3  30      80      70      180
Mode 4  25      70      40      125
Mode 5  20      50      25      100

                X address valid
                |        ___________            _____
DIOW-/DIOR-     |_______/           \__________/
                <--t1--> <---t2----> <---t2i--->
                         <----------t0--------->

NOTE:  t0 = t2 + t2i; however, the minimum values for t2 and t2i sum to
       less than t0.  Therefore, t2 and/or t2i must be extended as necessary
       to meet the minimum t0 requirement.


Below are the PCI-0640x register settings needed to achieve the various
PIO w/flow control modes at various local bus clock frequencies.  Note that
we have played it conservatively where the timings did not fit nicely into
integer multiples of the clock period.  Therefore, you can do further
tweaking via the PCI640X.EXE utility.

20Mhz Local Bus -> 50 ns/clock
--------------------------------------------------------
      |    REGISTER   | t1      t2      t2i     t0
      | ARTTIM  DWRTIM| ns(clks)ns(clks)ns(clks)ns(clks)
--------------------------------------------------------
Mode 0| 40h     47h   |100(2)   200(4)  400(8)  600(12)
Mode 1| 40h     34h   |100(2)   150(3)  250(5)  400(8)
Mode 2| 40h     22h   |100(2)   100(2)  150(3)  250(5)
Mode 3| 40h     21h   |100(2)   100(2)  100(2)  200(4)
min   | 40h     11h   |100(2)   100(2)  100(2)  200(4)
--------------------------------------------------------

25Mhz Local Bus -> 40 ns/clock
--------------------------------------------------------
      |    REGISTER   | t1      t2      t2i     t0
      | ARTTIM  DWRTIM| ns(clks)ns(clks)ns(clks)ns(clks)
--------------------------------------------------------
Mode 0| 40h     59h   | 80(2)   200(5)  400(10) 600(15)
Mode 1| 40h     45h   | 80(2)   160(4)  240(6)  400(10)
Mode 2| 40h     32h   | 80(2)   120(3)  120(3)  240(6)
Mode 3| 40h     22h   | 80(2)    80(2)  120(3)  200(5)
min   | 40h     11h   | 80(2)    80(2)   80(2)  160(4)
--------------------------------------------------------

33Mhz Local Bus -> 30 ns/clock
--------------------------------------------------------
      |    REGISTER   | t1      t2      t2i     t0
      | ARTTIM  DWRTIM| ns(clks)ns(clks)ns(clks)ns(clks)
--------------------------------------------------------
Mode 0| 80h     6dh   | 90(3)   180(6)  420(14) 600(20)
Mode 1| 40h     57h   | 60(2)   150(5)  240(8)  390(13)
Mode 2| 40h     43h   | 60(2)   120(4)  120(4)  240(8)
Mode 3| 40h     32h   | 60(2)    90(3)   90(3)  180(6)
Mode 4| 40h     31h   | 60(2)    90(3)   60(2)  150(5)
min   | 40h     11h   | 60(2)    60(2)   60(2)  120(4)
--------------------------------------------------------

40Mhz Local Bus -> 25 ns/clock
--------------------------------------------------------
      |    REGISTER   | t1      t2      t2i     t0
      | ARTTIM  DWRTIM| ns(clks)ns(clks)ns(clks)ns(clks)
--------------------------------------------------------
Mode 0| 80h     70h   | 75(3)   175(7)  425(17) 600(24)
Mode 1| 40h     5ah   | 50(2)   125(5)  275(11) 400(16)
Mode 2| 40h     45h   | 50(2)   100(4)  150(6)  250(10)
Mode 3| 40h     43h   | 50(2)   100(4)  100(4)  200(8)
Mode 4| 40h     31h   | 50(2)    75(3)   50(2)  125(5)
Mode 5| 40h     21h   | 50(2)    50(2)   50(2)  100(4)
min   | 40h     11h   | 50(2)    50(2)   50(2)  100(4)
--------------------------------------------------------

50Mhz Local Bus -> 20 ns/clock
--------------------------------------------------------
      |    REGISTER   | t1      t2      t2i     t0
      | ARTTIM  DWRTIM| ns(clks)ns(clks)ns(clks)ns(clks)
--------------------------------------------------------
Mode 0| 00h     d0h   | 80(4)   260(13) 340(17) 600(30)
Mode 1| 80h     7ch   | 60(3)   140(7)  260(13) 400(20)
Mode 2| 40h     56h   | 40(2)   100(5)  140(7)  240(12)
Mode 3| 40h     44h   | 40(2)    80(4)  100(5)  180(9)
Mode 4| 40h     42h   | 40(2)    80(4)   60(3)  140(7)
Mode 5| 40h     31h   | 40(2)    60(3)   40(2)  100(5)
min   | 40h     11h   | 40(2)    40(2)   40(2)   80(4)
--------------------------------------------------------

NOTE:  To achieve maximum throughput, it is also beneficial to increase the
       speed on the PCI-bus side.  Setting CNTRL (index 51) to 27h will
       1) disable host write fifo reg longer data hold time 2) enable fast
       DEVSEL timing 3) enable fast host write timing 4) enable fast host
       read timing.  If you want to tweak the IDE side timings, use
       PCI640X.EXE.



Example:  To set Mode 3 on the master drive on the primary IDE port on
          a 33MHz local bus:

   pci640x r 51 23  <- optional - specifies fastest host-side timing
   pci640x r 52 32
   pci640x r 53 40
   pci640x r 54 32

or, simply

   pci640x t 0 3
   pci640x r 51 23  <- optional - specifies fastest host-side timing


Don't forget to set your drive for Mode 3 operation via:

   pci640x d 0 3