The 6845 cathode ray tube controller is used on the PC for both monochrome and color video systems. The PS/2 VGA system provides some emulation for both of these controllers at the hardware level. The 6845 controller uses four I/O ports 3B4H, 3B5H, 3B8H, and 3BAH on the monochrome card (substitute 'D' for 'B' for color card). Port 3B4H is the 6845 index register, to which a control register value of 0 to 17 is sent before a read/write to the data register 3B5H. The 6845 has 18 control registers, 0-17. The first ten fix the horizontal and vertical display parameters. Incorrect settings of registers 1-9 can damage a monitor. Registers 10 and 11 set the shape of the cursor; 14 and 15 control its location. Registers 12 and 13 can handle scrolling. Numbers 16 and 17 report light pen position. Registers 12-15 are read/write. Registers 16-17 are read only. All other registers are write-only. 6845 Internal Registers: VGA Emulation and Extension: R0: Horizontal total characters (Total characters less 5) R1: Horizontal displayed characters (Display char./line -1) R2: Start Horizontal blanking R3: End Horizontal blanking R4: Vertical total lines Start Hor. Retrace Pulse R5: Vertical total adjust raster End Hor. Retrace R6: Vertical display line Vert. Total -2 (low 8 bits) R7: Vertical sync position line Overflow (see below) R8: Interlace: Preset Row Scan (see below) 00 10=non-interlace 01=duplicate 11=different R9: Maximum raster address Max. Scan Line (see below) R10: Cursor Start raster R11: Cursor End raster R12: Start address high R13: Start address low R14: Cursor high R15: Cursor low R16: Light pen high Vertical Retrace Start R17: Light pen low Vertical Retrace End (see below) R18: Vertical Display Enable End R19: Underline Location R20: Start Vertical Blank R21: End Vertical Blank R22: CRTC Mode Control R23: Line Compare The VGA emulation of the 6845 allows all registers to be read/write. Port 3B8H is a CRT control port: Bit Function PS/2 Emulation: None 7-6 Reserved 5 Blink enable 4 Reserved 3 Video enable 2-1 Reserved 0 High resolution mode Port 3BAH is a CRT read/only status port and a write/only feature control port on the PS/2. As a read/only port: Bit Function PS/2 Extension: Input Status Register 1 7-6 Reserved Reserved 5 Reserved Attribute controller diagnostic 0 4 Reserved Attribute controller diagnostic 1 3 Video dots Vertical retrace 2-1 Reserved Reserved 0 Horizontal sync Display enable (1=hor. or vert. retrace) As a write/only port on the PS/2, the Write Feature Control Register, all bits are reserved (bit 3 must be 0). On the Hercules Graphics Controller, bit 7 may be used to distinguish a Hercules card from an IMB Monochrome or Color Adapter. On the Hercules card, bit 7 goes 0 on vertical retrace (50 Hz). On the IBM card, bit 7 does not change. The Hercules and the Hercules Plus can be distinguished with bits 4 and 5 (1 and 0 for Plus). ____________________________________________________________________________ ---------------------------------------------------------------------------- Ports: 3C0H-3CFH: VGA Support ---------------------------------------------------------------------------- In addition to emulation for the 6845 status, index, and control ports, the VGA system on the PS/2 uses the ports 3C0H-3CFH for additional video status information and control. Input Status Register 1: 3BAH or 3DAH: (R) Bit Function 7-6 Reserved = 0 5-4 Diagnostic 0,1 Selectively connected to two of eight 3 Vertical Retrace 2-1 Reserved = 0 0 Display Enable Attribute Registers: 3C0H-3C1H: 0 Attribute Controller Registers: Bit Function 7-6 Reserved = 0 5 Palette Address Source (Set 0 when loading color palette registers) 4-0 Attribute Address Each attribute data register is written at 3C0H and read from 3C1H. To initialize the address flip-flop, issue IOR to 3BAH or 3DAH. Then load the attribute controller register. This toggles the flip-flop for a OUT to the indexed data register. The flip-flop is not toggled by a read from 3C1H. Palette Registers: Index 00 to 0FH: Bit Function 7-6 Reserved = 0 5-0 P5-P0 Used to map color input to display color Attribute Mode Control Register: Index 10H: Bit Function 7 P5, P4 Select 1=source from bits 1,0 of Color Select Register 6 PEL Width - 1 for 256-color mode 5 PEL Panning Compatibility 4 Reserved = 0 3 Select Background Intensity 2 Enable Line Graphics Character Code (0=ninth dot same as backgnd) 1 Mono Emulation 0 Graphics/Alphanumeric Mode (1=graphics) Overscan Color Register: Index 11H: Bit Function 7-0 P7-P0 Border color Color Plane Enable Register: Index 12H: Bit Function 7-6 Reserved = 0 5-4 Video Status MUX - Selects 2 of 8 color outputs for status port 3-0 Enable Color Plane Horizontal PEL Panning Register: Index 13H: Bit Function 7-4 Reserved = 0 3-0 Horizontal PEL Panning (number of pixels to pan) Color Select Register: Index 14H: Bit Function 7-4 Reserved = 0 3-2 S_color76 - two high-order bits of 8 bit color value 2-0 S_color54 - replaces P5 and P4 in Attrib.Palette Reg. Read Input Status Register 0: 3C2H: (R) Bit Function 7 CRT interrupt 1 = vertical retrace interrupt pending 6-5 Reserved 4 Switch Sense Bit: Lets POST determine monochrome or color 3-0 Reserved Write Misc. Output Register: 3C2H: (W) Read Misc. Output Register: 3CCH: (R) Bit Function 7 Vert. sync polarity 0 = positive retrace 6 Hor. sync polarity 0 = positive retrace bits 7,6= 1 0 for 400 lines 0 1 for 350 lines 1 1 for 480 lines 5 Page bit for odd/even (dianostic use) 1 = high 64K page 4 Reserved = 0 3-2 Clock select 0 0 = 25.175 MHz for 640 hor. pixels 0 1 = 28.322 MHz for 720 hor. pixels 1 0 = external clock at aux. video input (14.3-28.4 MHz) 1 1 = reserved 1 Enable RAM 0 = disable video RAM address decode from CPU 0 I/O address select - CRTC I/O 0 = 3BxH, 1 = 3DxH Video Subsystem Enable: 3C3H: Bit Feature 7-1 Reserved 0 Video subsystem enable: 1 = video I/O and memory address decoding is enabled. This register is not affected by the VGA sleep bit (102H bit 0). Sequencer Registers: 3C4H-3C5H: Sequencer Address Register: 3C4H: This register is loaded with a index to the following Sequence Data registers: Sequence Data Registers: 3C5H: Reset Register (R/W) (Index 0): Bit Function 7-2 Reserved 1 Synchronous reset 0 = synchr. clear and halt (before Clocking Mode register bit 0 or Misc. Output Register bit 2) 0 Asynchronous reset 0 = asynchr. clear and halt Clocking Mode Register (R/W) (Index 1): Bit Function 7-6 Reserved = 0 5 Screen off 1 = screen off (use for rapid full-screen update by giving CPU maximum memory bandwidth) 4 Shift 4 0 = video serializers are loaded every char. clock, 1 = video serializers loade every fourth clock (use with 32 bit fetches/cycle) 3 Dot clock 0 = select normal dot clock, 1 = master clock/2 (clock/2 used for 320 and 360 hor. pixel modes) 2 Shift load: if 0 and if bit 4=0, video serializers reloaded every char. clock, when 1, every other char. clock (use with 16 byt fetches/cycle) 1 Reserved = 0 0 8/9 dot clocks 0 = char. clocks 9 dots wide. Map Mask Register (R/W) (Index 2): Bit Function 7-4 Reserved = 0 3 Map 3 enable 1 = CPU can write to map 3 2 Map 2 enable 1 Map 1 enable 0 Map 0 enable If this register is set to 0FH, the system microprocessor can perform 32 bit wide write in only one memory cycle. Character Map Select Register (R/W) (Index 3): Bit Function 7-6 Reserved = 0 5 Character Map select high bit A 4 Character Map select high bit B 3-2 Character Map select A 1-0 Character Map select B In alphanumeric modes, bit 3 of the attribute byte normally is used to control foreground intensity. This bit may be redefined, however, to switch between character sets. For this feature to be enabled, the following must be true: Memory Mode register bit 1 = 1 Character Map Select A is not the same as Character Map Select B If either is not true, the first 16K of Map 2 is used. For selection A: Bit 5 3 2 Map Table Location 0 0 0 0 1st 8K of Map 2 0 0 1 1 3rd 8K of Map 2 0 1 0 2 5th 8K of Map 2 0 1 1 3 7th 8K of Map 2 1 0 0 4 2nd 8K of Map 2 1 0 1 5 4th 8K of Map 2 1 1 0 6 6th 8K of Map 2 1 1 1 7 8th 8K of Map 2 Similarly for selection B using bits 4, 1, and 0. Memory Mode Register (R/W) (Index 4) Bit Function 7-4 Reserved = 0 3 Chain 4 0 = enable CPU to access data at addresses within bit map using Map Mask register. 1 = enable CPU to access data at addresses according to two low order bits of address A1, A0: 00=map 0, 01=map 1, 10=map 2, 11=map 3. 2 Odd/even 0 = use maps 0,2 or 1,3 according to parity of address. 1 = access data sequentially using Map Mask register 1 Extended memory 1 = greater than 64K video memory present 0 Reserved = 0 Digital to Analog Converter Registers: 3C6H-3C9H: 3C6H R/W: Pixel Mask (color look-up table destroyed on write) 3C7H Read: DAC State Register 3C7H Write: Pixel Address 3C8H R/W: Pixel Address Read Feature Control Register: 3CAH: All bits reserved. Miscellaneous Output Register: 3CCH (R) See port 3C2h. Graphics Registers: 3CEH-3CFH: Graphics Controller Registers: 3CEH: This read/write register is loaded with the index to the graphic registers described below: Graphics Registers (R/W) 3CFH: Set/Reset Register (R/W) (Index 0): Bit Function 7-4 Reserved = 0 3 Set/Reset Map 3 2 Set/Reset Map 2 1 Set/Reset Map 1 0 Set/Reset Map 0 Enable Set/Reset Register (R/W) (Index 1): Bit Function 7-4 Reserved = 0 3 Enable Set/Reset Map 3 2 Enable Set/Reset Map 2 1 Enable Set/Reset Map 1 0 Enable Set/Reset Map 0 Color Compare Register (R/W) (Index 2): Bit Function 7-4 Reserved = 0 3 Color Compare Map 3 2 Color Compare Map 2 1 Color Compare Map 1 0 Color Compare Map 0 Data Rotate Register (R/W) (Index 3): Bit Function 7-5 Reserved = 0 4-3 Function Select 00 Data unmodified, 01 ANDed, 10 ORed, 11 XORed 2-0 Rotate Count for right-rotate (write mode 0) ReadMap Select Register (R/W) (Index 4): Bit Function 7-2 Reserved = 0 1-0 Map Select for read Graphics Mode Register (R/W) (Index 5): Bit Function 7 Reserved = 0 6 256 color mode: 0=allow bit 5 to control loading of Shift registers 5 Shift Register Mode: 1=format serial data with even-numbered bits for even maps odd-numbered bits for odd maps 4 Odd/Even: 1=odd/even addressing mode 3 Read Type: 0=reads from memory map selected by Read Map Select Reg. 2 Reserved 1-0 Write Mode for memory map: 00=data rotated unless Set/Reset is enabled 01=from contents of system CPU latches 10=map n (0-3) filled with 8 bits of data bit n 11=from 8 bits in Set/Reset register for that map Miscellaneous Register (R/W) (Index 6): Bit Function 7-4 Reserved = 0 3-2 Memory Map: 00=A0000 for 128K bytes 01=A0000 for 64K bytes 10=B0000 for 32K bytes 11=B8000 for 32K bytes 1 Odd/Even: 1=use odd/even maps for odd even addresses 0 Graphics Mode: 1=graphics mode, 0=alphanumeric mode Color Don't Care Register (R/W) (Index 7): Bit Function 7-4 Reserved = 0 3 Map 3 - Don't Care (0=Don't participate in color compare cycle) 2 Map 2 - Don't Care 1 Map 1 - Don't Care 0 Map 0 - Don't Care Bit Mask Register (R/W) (Index 8): Bit Function 7-0 Mask: 0=bit n in each map to be immune to change (modes 0 and 2)